3D Processor Architecture for Parallel Computing Density
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Solution Overview
Problem
Conventional processors are limited in computational density and complexity due to their reliance on two-dimensional integration, which restricts the implementation of non-arithmetic functions and results in inefficient scientific computations, especially in fields like computational mathematics and physics.
Innovation Solution
A three-dimensional processor architecture that integrates arithmetic logic circuits with a three-dimensional memory array, enabling the direct hardware implementation of non-arithmetic functions through a larger look-up table capacity and parallel processing, thereby enhancing computational density and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two-dimensional integration is used to implement built-in functions with LUTs, then the processor can support basic non-arithmetic functions, but the die size increases and computational density decreases
Solution Approach 1:
The patent transitions from two-dimensional integration to three-dimensional integration by stacking multiple processor layers vertically. This allows the LUT to be implemented in the third dimension (vertical stacking) rather than occupying horizontal die area, thereby increasing the number of supported built-in functions without proportionally increasing die size. The 3D integration enables higher computational density by utilizing vertical space for function implementation.
2Adaptability or versatility
If LUT is included in conventional processor, then non-arithmetic functions can be implemented, but computational density is lowered due to increased die size
Solution Approach 1:
By moving from 2D to 3D integration, the patent enables the LUT to be stacked vertically above the ALU rather than placed side-by-side on the same plane. This vertical arrangement allows both the ALU and LUT to occupy overlapping horizontal footprints, effectively doubling the functional density without increasing die area. The computational density increases because the same physical footprint now supports both arithmetic and non-arithmetic functions simultaneously in the vertical dimension.
3Power
If ALU occupies large die area in conventional processor, then arithmetic operations are performed, but LUT is left with small die area and supports few built-in functions
Solution Approach 1:
The patent resolves the spatial conflict between ALU and LUT by stacking them in the vertical dimension. The ALU remains in the first layer performing arithmetic operations, while the LUT is stacked in subsequent layers above it. This 3D arrangement allows both components to have adequate functional capacity without competing for horizontal die area, enabling the processor to support both powerful arithmetic operations and a comprehensive set of built-in functions simultaneously.
4Device complexity
If 2-D integration is used, then processor structure is simple, but computational complexity and density are severely limited
Solution Approach 1:
The patent enhances computational density by adding the vertical dimension to the traditional 2D processor architecture. Multiple functional layers (ALU, LUT, interconnect structures) are stacked vertically with controlled inter-layer connections. While this increases structural complexity compared to 2D integration, the gain in computational density and functional integration far outweighs the moderate increase in manufacturing and design complexity.
Data Source
AI summary
A three-dimensional processor (3D-processor) for parallel computing includes a plurality of computing elements. Each computing element comprises at least a three-dimensional memory (3D-M) array for storing at least a portion of a look-up table (LUT) for a mathematical function and an arithmetic logic circuit (ALC) for performing arithmetic operations on the LUT data. Deficiency in latency is offset by a large scale of parallelism.