3D Processor Stacking with Local Cooling and Global Interconnects
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Solution Overview
Problem
As the number of processors on a chip increases, on-chip communication between processors becomes problematic due to increased cycle delays and the need for high-powered drivers, and implementing effective global interconnect schemes and cooling structures becomes expensive and challenging in multi-chip systems.
Innovation Solution
A three-dimensional computer processor system is developed, where multiple multi-chip systems are aggregated with local power and cooling layers, and a global interconnect structure connects these systems, utilizing short vertical interconnects to align and connect processor chips across layers, allowing for efficient communication and resource sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processors per chip is increased to accommodate more processors, then processing capacity is improved, but communication cycle delay between processors increases and high-powered drivers are required
Solution Approach 1:
The patent transitions from a two-dimensional processor arrangement to a three-dimensional stacked architecture. Multiple processor chips are stacked vertically and interconnected through short vertical wires, enabling processors to communicate across layers with minimal delay. This dimensional change allows high processing capacity while maintaining short communication paths.
2Productivity
If the 2-D size of the processor chip is increased to accommodate more processors, then processing capacity is improved, but the length of horizontal wiring between processors increases resulting in cycle delays
Solution Approach 1:
The patent replaces long horizontal wiring in 2-D layouts with short vertical interconnects in a 3-D stacked architecture. Processors on different chips communicate through vertical wires that traverse the stack height, which is much shorter than horizontal distances across a large 2-D chip. This dramatically reduces wiring length while maintaining high processor density.
3Productivity
If integration density is increased in multi-chip systems, then processing capacity is improved, but implementing global interconnect schemes becomes expensive and challenging
Solution Approach 1:
The patent divides the interconnect system into local and global components. Local interconnects handle communication within each processor chip, while a global interconnect network connects the stacked chips. This segmentation simplifies the design by breaking down the complex global interconnection problem into manageable local and global layers, reducing overall system complexity.
4Productivity
If integration density is increased in multi-chip systems, then processing capacity is improved, but implementing effective cooling structures becomes expensive and challenging
Solution Approach 1:
The patent introduces vertical cooling channels that traverse through the stacked processor chips. Cooling fluid flows through these vertical passages, efficiently removing heat from high-density processor regions. This 3-D cooling approach is more effective than traditional 2-D heat sinks, as it provides direct thermal access to processors throughout the stack, enabling high integration density with effective heat management.
Data Source
AI summary
A computer processor system includes a plurality of multi-chip systems that are physically aggregated and conjoined. Each multi-chip system includes a plurality of chips that are conjoined together, and a local interconnection and input/output wiring layer. A global interconnection network is connected to the local interconnection and input/output wiring layer of each multi-chip system to interconnect the multi-chip systems together. One or more of the multi-chip systems includes a plurality of processor chips that are conjoined together.