3D PUF Key Generation Circuit for Stable Chip Identification
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Solution Overview
Problem
Existing identification key generation methods for semiconductor devices face challenges in achieving high stability and time invariance due to temperature and voltage variations, and are vulnerable to intrusion attacks, leading to increased costs and reduced economic efficiency.
Innovation Solution
An identification key generation circuit based on process deviation in a monolithic three-dimensional semiconductor manufacturing process, utilizing a first and second semiconductor element portion with different physical characteristics, connected through via-holes and metal wiring, to generate a stable and secure identification key using differences in electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If process variations in CMOS production process are used to generate PUF identification keys, then unique device identification is achieved, but stability and time invariance are compromised due to temperature and voltage variations
Solution Approach 1:
The patent transitions from two-dimensional planar transistor structures to three-dimensional vertically stacked transistor structures. This dimensional change increases the magnitude of process variations in critical dimensions, thereby enhancing the uniqueness and stability of PUF-generated identification keys while maintaining resistance to environmental variations.
Solution Approach 2:
The patent introduces deliberate local asymmetries in the vertical stacking configuration, such as varying the number of transistors in different stacks or adjusting interconnect positions. These localized structural differences amplify process variation effects in specific regions, improving the distinguishability and stability of the generated identification keys.
2Reliability
If separate intrusion attack detection circuits are added to prevent PUF key theft, then security is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the PUF key generation function with the security protection function into a single integrated structure. The vertical stacked transistor configuration inherently provides both the unique identification key generation and resistance to intrusion attacks, eliminating the need for separate detection circuits and reducing overall device complexity.
Solution Approach 2:
The vertically stacked transistor structure serves multiple functions simultaneously: it generates unique identification keys through process variations, provides inherent security against intrusion attacks through its three-dimensional configuration, and maintains compact form factor. This multi-functionality eliminates the need for additional dedicated security circuits.
3Quantity of substance
If traditional scaling down is continued to increase integration, then component density improves, but economic, physical, and technical limits are reached at 10 nm level
Solution Approach 1:
The patent employs three-dimensional vertical stacking of transistors instead of continuing traditional two-dimensional scaling. This approach achieves higher component density by utilizing the vertical dimension, thereby avoiding the physical and technical limits encountered at 10 nm node planar scaling while maintaining manufacturing feasibility.
Data Source
AI summary
An identification key generation circuit using process deviation comprises a first semiconductor element portion and a second semiconductor element portion manufactured on a single semiconductor substrate and have different physical characteristics, an identification key generation portion generating an identification key using at least one of a difference in electrical characteristics of the first semiconductor element portion due to a process deviation occurring in the manufacturing process of the first semiconductor element portion and an identification key derivation portion determining the difference in electrical characteristic as a digital value, wherein the first semiconductor element portion is formed on the semiconductor substrate, and the second semiconductor element portion is formed on the upper portion of the first semiconductor element portion, and wherein the first semiconductor element portion and the second semiconductor element portion are connected to each other through at least one layer of via-holes, metal wiring, and contact hole layers.