3D RDL Semiconductor Packaging With Embedded Cavity Interconnects
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Solution Overview
Problem
Conventional semiconductor packages face issues of excess cost, decreased reliability, and large package sizes, leading to inadequate performance.
Innovation Solution
The development of semiconductor devices with a first and second redistribution layer (RDL) substrate, each comprising dielectric and conductive structures, and internal interconnects, along with a manufacturing method involving carrier inversion and singulation processes to enhance electrical coupling and protection of electronic components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packages are used, then manufacturing is simpler, but cost is excessive and reliability is decreased
Solution Approach 1:
The semiconductor package is divided into multiple functional layers including first and second RDL substrates, dielectric structures, conductive structures, and internal interconnects. Each layer performs specific functions and can be manufactured and tested independently before final assembly, improving reliability while enabling modular manufacturing processes.
Solution Approach 2:
The patent implements a nested structure where electronic components are embedded within dielectric structures, which are in turn surrounded by conductive structures and internal interconnects. This nested arrangement protects components while maintaining compact packaging that reduces overall device size and cost.
2Volume of moving object
If conventional package structures are used, then manufacturing is easier, but package size is too large
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacking with multiple RDL substrates arranged vertically. Internal interconnects extend through dielectric structures to provide electrical connections between layers, enabling compact packaging that reduces footprint while maintaining manufacturing feasibility through standardized layer-by-layer construction.
Solution Approach 2:
Electronic components are nested within dielectric structures that are themselves nested within conductive structures and internal interconnect systems. This nested configuration maximizes space utilization and minimizes package volume while maintaining ease of manufacture through systematic assembly procedures.
3Reliability
If conventional packages are used, then structure is simpler, but performance is low
Solution Approach 1:
The device is segmented into functionally distinct layers: first RDL substrate for input signals, second RDL substrate for output signals, dielectric structures for insulation and component mounting, conductive structures for electrical pathways, and internal interconnects for inter-layer communication. This segmentation improves performance by reducing signal interference and enabling optimized signal routing, while the modular nature manages structural complexity.
Solution Approach 2:
The patent utilizes vertical stacking of multiple RDL substrates with internal interconnects providing three-dimensional electrical pathways. This dimensional transition enables shorter signal paths, reduced parasitic effects, and improved signal integrity compared to conventional planar packages, thereby enhancing device performance despite increased structural complexity.
Data Source
AI summary
In one example, a semiconductor device comprises a first substrate comprising a first conductive structure, a first body over the first conductive structure and comprising an inner sidewall defining a cavity in the first body, a first interface dielectric over the first body, and a first internal interconnect in the first body and the first interface dielectric, and coupled with the first conductive structure. The semiconductor device further comprises a second substrate over the first substrate and comprising a second interface dielectric, a second body over the second interface dielectric, and a second conductive structure over the second body and comprising a second internal interconnect in the second body and the second interface dielectric. An electronic component is in the cavity, and the second internal interconnect is coupled with the first internal interconnect. Other examples and related methods are also disclosed herein.