3D Redistribution Circuit Structure for Reliable Tier-to-Tier Interconnects
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving efficient miniaturization, higher speed, greater bandwidth, lower power consumption, and reduced latency due to limitations in current packaging techniques for semiconductor dies, particularly in creating reliable and efficient electrical connections between multiple tiers of semiconductor dies in 3D packaging.
Innovation Solution
A semiconductor structure is developed with a routing structure that includes vertical and horizontal electrical structures, where multiple tiers of semiconductor dies are bonded and electrically connected through a redistribution circuit structure, using hybrid bonding interfaces and through vias to enhance electrical communication and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple tiers of semiconductor dies are bonded together in 3D packaging, then functional density and bandwidth are improved, but manufacturing complexity and reliability of electrical connections deteriorate
Solution Approach 1:
The patent divides the interconnection system into distinct segments: routing structures with conductive traces on substrates, separate semiconductor dies, and modular bonding interfaces. This segmentation allows each component to be manufactured and tested independently before assembly, reducing overall manufacturing complexity while enabling high functional density through precise stacking of multiple tiers.
Solution Approach 2:
The patent transitions from traditional 2D planar packaging to 3D vertical stacking by introducing routing structures that extend in the vertical dimension. Conductive traces and bonding interfaces are arranged across multiple tiers stacked along the vertical axis, enabling increased functional density and bandwidth without proportionally increasing lateral packaging complexity.
2Productivity
If multiple tiers of semiconductor dies are bonded together in 3D packaging, then bandwidth is improved, but reliability of electrical connections deteriorates
Solution Approach 1:
The patent implements preliminary bonding of routing structures to semiconductor dies before final tier assembly. Bonding interfaces are prepared and positioned in advance with aligned conductive traces and bonding pads, ensuring reliable electrical connections are established prior to the complexity of multi-tier stacking. This preliminary action reduces connection reliability issues in the final 3D structure.
Solution Approach 2:
The patent introduces routing structures as intermediary components between semiconductor dies. These routing structures with conductive traces act as mediators that establish and maintain reliable electrical connections across multiple tiers, distributing connection points and reducing the complexity of direct die-to-die bonding interfaces.
3Reliability
If hybrid bonding interfaces and through vias are used, then electrical connection reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the bonding interface into distinct functional zones: hybrid bonding regions with both dielectric and metal bonding, and through via regions for vertical electrical connections. This segmentation allows each bonding feature to be optimized and manufactured using specialized processes independently, improving electrical connection reliability while managing overall manufacturing complexity through modular fabrication steps.
Data Source
AI summary
A semiconductor structure includes a first tier, a redistribution circuit structure, and a second tier. The first tier includes at least one first die. The redistribution circuit structure is disposed on the first tier and electrically coupled to the at least one first die, where the redistribution circuit structure has a multi-layer structure and includes a vertical connection structure continuously extending from a first side of the redistribution circuit structure to a second side of the redistribution circuit structure, and the first side is opposite to the second side along a stacking direction of the first tier and the redistribution circuit structure. The second tier includes a plurality of second dies, and is disposed on and electrically coupled to the redistribution circuit structure. The redistribution circuit structure is disposed between the first tier and the second tier, where the at least one first die is electrically connected to and electrically communicated with the plurality of second dies through the redistribution circuit structure, and the plurality of second dies are electrically connected to and electrically communicated with each other through the redistribution circuit structure.