3D Register-Integrated Memory Structure for Lower-Power Arithmetic Circuits
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing power consumption and circuit layout area due to data transfer between external memory and registers, which leads to increased energy consumption and layout overhead.
Innovation Solution
Incorporating a stacked structure of OS transistors and capacitors over registers, with dielectric and semiconductor layers perpendicular to the substrate, to enhance memory capacity and reduce layout area while minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is temporarily written to external memory when register bank lacks processing capacity, then processing capability is improved, but energy consumption increases due to writing and writing back data
Solution Approach 1:
The patent integrates memory cells directly within the register bank structure, nesting storage functionality inside the processing unit. This eliminates the need for external memory access during task switching, as context data can be retained within the nested memory cells of the same register bank, thereby avoiding energy-consuming data transfer operations.
Solution Approach 2:
The patent combines register and memory functions into a unified structure where memory cells are integrated with register circuits. This merging allows the register bank to simultaneously perform processing and data retention functions, eliminating the separate external memory access path and reducing energy consumption associated with data writing and reading.
2Use of energy by moving object
If a large number of register banks are prepared to inhibit energy consumption, then energy consumption due to data transfer is reduced, but circuit layout area increases
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional vertical structure by stacking memory cells over registers. This dimensional change allows multiple memory cells to occupy the same footprint area, effectively increasing storage capacity without proportionally increasing the circuit layout area, thus enabling more register banks to be implemented with reduced area overhead.
Solution Approach 2:
The patent nests memory cells within the vertical space above register circuits, allowing memory functionality to be embedded within the register bank structure. This nesting approach enables the co-location of storage and processing elements without requiring additional lateral space, thereby supporting multiple register banks with minimized circuit layout area.
3Quantity of substance
If memory cells are integrated over registers in a stacked structure, then memory capacity per unit area is increased, but device structure complexity increases
Solution Approach 1:
The patent employs vertical stacking to increase memory capacity per unit area by utilizing the third dimension (height) rather than expanding in the planar directions. Memory cells are formed above registers through vertical deposition and patterning processes, achieving higher integration density without proportionally increasing manufacturing complexity by leveraging standard semiconductor vertical fabrication techniques.
Data Source
AI summary
A semiconductor device including a flip-flop circuit and a memory circuit is provided. The memory circuit includes a first transistor, a second transistor, a first capacitor, and a second capacitor. The semiconductor device includes a substrate, a first insulator, and a second insulator. The first insulator includes a first opening and a second opening. The second insulator includes a third opening and a fourth opening. The flip-flop circuit is provided over the substrate. At least parts of the first capacitor and the second capacitor are provided in the first opening portion and the second opening portion, respectively. At least parts of the first transistor and the second transistor are provided in the third opening portion and the fourth opening portion, respectively.