3D ReRAM Memory Device Architecture for High Integration

The patent transitions from planar 2D memory cell arrangements to a 3D vertical architecture where memory cells are stacked across multiple layers. Column lines extend vertically through multiple memory cell layers, and select gate lines are positioned at different vertical levels, enabling high-density storage without proportionally increasing chip area. This dimensional change allows multiple memory cells to be integrated in the vertical direction, significantly improving integration density.

The memory device is divided into multiple memory cell layers stacked vertically, with each layer containing an array of memory cells. Select gate lines are segmented and positioned at different vertical levels to control specific layers. This segmentation allows independent control of different memory layers, enabling high-density integration while maintaining manageable control complexity through modular layer management.

The patent applies different voltage levels to different line types to create localized control zones. Selected word lines receive high voltage (e.g., 3.0V) for strong selection, while non-selected word lines receive low voltage (e.g., 0.0V). Similarly, selected bit lines receive high voltage while non-selected bit lines receive low voltage. This local quality differentiation ensures that only memory cells at the intersection of selected word and bit lines experience sufficient voltage to undergo resistance change, preventing unintended modification of non-selected cells.

The memory device dynamically adjusts voltage levels applied to word lines and bit lines based on selection status. During write operations, the controller dynamically switches selected word lines and bit lines to high voltage states while keeping non-selected lines at low voltage. This dynamic voltage control creates time-dependent selection windows that precisely control which memory cells are affected, ensuring data is written only to intended target cells while maintaining reliability.

The patent incorporates sense amplifiers that provide feedback control for read operations. During reading, the sense amplifier detects the resistance state of selected memory cells by measuring current flow through the selected word line and bit line intersection. The sense amplifier compares the detected signal against reference levels and provides feedback to the controller, enabling precise determination of the memory cell state. This feedback mechanism ensures accurate reading of resistance states without causing unintended changes, maintaining ease of operation despite using resistance change materials.

The patent employs specific voltage thresholds to control resistance state transitions in memory cells using resistance change materials. Write operations apply high voltage (e.g., 3.0V) to selected word lines and bit lines to induce resistance changes from high-resistance to low-resistance states. Read operations use lower voltage levels that are sufficient to detect resistance states but below the threshold for inducing changes. This parameter control strategy enables precise manipulation of resistance states, facilitating ease of operation while achieving high integration capacity through the use of resistance change materials.