3D ReRAM Memory Device Segmentation and Data Correction
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Solution Overview
Problem
Three-dimensional ReRAM memory devices face challenges in suppressing interference between memory cells, which affects access speed and bit error rates during read operations due to parasitic capacitance and resistance differences between global bit lines and word lines.
Innovation Solution
The memory device employs a selection circuit with row and global bit line selection, a data processing system that includes pre-processing and post-processing circuits to correct data differences, and a specific bias voltage configuration to manage the resistance varying material's states, reducing interference through precise voltage control and data processing algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional stacking structure is used to improve integration degree, then manufacturing density increases, but interference between memory cells increases
Solution Approach 1:
The memory device segments the bit lines into multiple independent global bit lines (GBL0, GBL1, GBL2, GBL3) that are selectively activated. This segmentation allows the memory array to be divided into separate access regions, preventing interference between memory cells accessed simultaneously through different global bit lines, while maintaining high integration density through the 3D stacking structure.
Solution Approach 2:
Selection elements (transistors) are introduced as intermediary components between the global bit lines and the memory cells. These selection elements act as mediators that control and isolate current flow, enabling selective access to specific memory cells while blocking interference paths to other cells. The selection elements gate the connection between global bit lines and column lines, preventing parasitic current leakage that would cause interference.
2Quantity of substance
If three-dimensional stacking structure is used to improve integration degree, then memory density increases, but access speed decreases
Solution Approach 1:
The memory device segments the bit lines into multiple independent global bit lines (GBL0, GBL1, GBL2, GBL3) that are selectively activated. This segmentation allows the memory array to be divided into separate access regions, preventing interference between memory cells accessed simultaneously through different global bit lines, while maintaining high integration density through the 3D stacking structure.
Solution Approach 2:
The selection circuit pre-selects the appropriate global bit line and word line combination before the actual read/write operation. By preliminarily establishing the correct electrical paths and activating only the necessary selection elements, the system minimizes setup time and avoids the need to deactivate and reconfigure paths during operations, thereby improving access speed despite the complex 3D structure.
3Quantity of substance
If global bit lines and word lines are used in three-dimensional structure, then data storage capacity increases, but voltage differences and interference increase
Solution Approach 1:
A data processing system with pre-processing and post-processing circuits is implemented to detect and correct voltage differences and interference effects. The pre-processing circuit adjusts write voltages to compensate for predicted interference, while the post-processing circuit reads the actual cell state and corrects any errors, ensuring data integrity is maintained despite the presence of parasitic capacitance and resistance in the global bit lines and word lines.
Solution Approach 2:
The selection circuit dynamically changes electrical parameters (voltage levels, current directions) applied to different global bit lines and word lines based on the specific access pattern. By adjusting these parameters in real-time, the system optimizes signal integrity for each operation and minimizes parasitic effects, maintaining reliable data storage and retrieval across the high-capacity three-dimensional memory array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances data integrity and access speed by minimizing interference between cells, improving bit error rates and tolerance to noise, even under conditions of high noise levels.
Implementation Method 1
a memory cell array including: row lines that are aligned in a two-dimensional array shape in the Y direction and the Z direction and extend in the X direction; column lines that are aligned in a two-dimensional array shape in the X direction and the Y direction and extend in the Z direction... a selection circuit... a data processing circuit
Data Source
AI summary
A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.