3D Resist Profile Aware Etch-Bias Model for Semiconductor Manufacturing
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Solution Overview
Problem
Conventional 2D etch models fail to accurately predict etching distortions and wafer patterning issues in deep submicron semiconductor manufacturing, leading to inaccuracies and increased time-to-market, as they do not consider 3D resist profile information, resulting in deteriorated wafer yield.
Innovation Solution
A 3D resist profile aware etch-bias model is developed, incorporating a sidewall slope term to capture non-vertical resist sidewall effects, which is used to compute etch biases and adjust patterns for improved accuracy and efficiency in semiconductor manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional 2D etch models are used, then the manufacturing process is simple and fast, but the etching distortion prediction accuracy deteriorates
Solution Approach 1:
The patent transitions from 2D etch models to 3D resist profile aware etch-bias models by incorporating the sidewall slope dimension. The model now considers the third dimension (sidewall slope angle) to accurately predict etching distortions, which cannot be captured by conventional 2D models. This dimensional expansion enables precise prediction of how non-vertical sidewalls affect etch bias.
Solution Approach 2:
The patent introduces new parameters including sidewall slope angle and resist profile characteristics into the etch-bias model. By changing the model parameters from simple 2D geometric features to 3D resist profile parameters, the model gains the capability to accurately predict etching distortions while maintaining computational efficiency through optimized parameter selection.
2Measurement precision
If 3D resist profile aware etch-bias model is used, then the etching distortion prediction accuracy is improved, but the computational time increases
Solution Approach 1:
The patent performs preliminary computation of resist profile characteristics and sidewall slope angles before the etch-bias calculation. By pre-calculating these 3D profile parameters from the developed resist pattern, the model avoids repeated complex 3D simulations during etch prediction, thus reducing overall computational time while maintaining high accuracy.
Solution Approach 2:
The patent segments the computational process into distinct stages: first calculating resist profile and sidewall slope from lithography patterns, then using these pre-computed 3D parameters for etch-bias prediction. This segmentation allows efficient reuse of calculated parameters across multiple evaluation points, reducing redundant computations.
3Productivity
If conventional 2D etch models are used, then the processing speed is fast, but the wafer yield deteriorates due to inaccurate predictions
Solution Approach 1:
The patent incorporates 3D resist profile information including sidewall slope angle into the etch-bias model, enabling accurate prediction of etching distortions that directly impact wafer yield. This dimensional enhancement allows the model to capture the true physics of non-vertical sidewall etching, leading to better yield outcomes.
Solution Approach 2:
The patent changes the model parameters to include sidewall slope angle and resist profile characteristics, which are critical for predicting etch-induced yield losses. By using these physically meaningful parameters, the model provides accurate yield predictions without requiring excessive complexity.
4Manufacturing precision
If sidewall slope term is incorporated in etch-bias model, then the resist profile accuracy is improved, but the model complexity increases
Solution Approach 1:
The patent introduces sidewall slope angle as a key parameter in the etch-bias model, directly linking resist profile geometry to etch outcomes. This parameter change enables accurate representation of non-vertical sidewalls and their impact on etch bias, improving manufacturing precision while keeping the model structure manageable.
Solution Approach 2:
The patent pre-calculates sidewall slope angles from the developed resist pattern before feeding them into the etch-bias model. This preliminary computation of geometric parameters simplifies the main etch-bias calculation by providing ready-to-use 3D profile information, reducing the complexity burden during the critical etch prediction phase.
Data Source
AI summary
Systems and techniques for three-dimension (3D) resist profile aware resolution enhancement techniques are described. 3D resist profile aware resolution enhancement models can be calibrated based on empirical data. Next, the 3D resist profile aware resolution enhancement models can be used in one or more applications, including, but not limited to, lithography verification, etch correction, optical proximity correction, and assist feature placement.