3D Resist Profile Modeling for Lithography Process Variation
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Solution Overview
Problem
As semiconductor device fabrication progresses, the miniaturization of patterns on substrates leads to distortions and deviations due to interference and processing effects in optical lithography, resulting in improperly reproduced patterns that can cause devices to malfunction or fail to meet design specifications, increasing production costs and reducing yield.
Innovation Solution
A method involving the generation of three-dimensional (3-D) resist profiles for different process conditions using a processor, combining these profiles to create a 3-D process variation band profile, which helps visualize and correct lithographic process variations, allowing for improved ground rule development, layout optimization, and process optimization before mask fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If optical lithography is used to reproduce patterns with dimensions smaller than the wavelength of light, then the resolution and precision of pattern reproduction deteriorate due to interference and processing effects, but using longer wavelengths would increase the wavelength itself and further worsen the resolution
Solution Approach 1:
The patent applies preliminary action by performing 3-D resist profile simulations and process variation analysis before actual mask fabrication. Multiple 3-D resist profiles are generated for different process conditions (focus, dose, mask bias) and combined to create 3-D process variation band profiles. This preliminary virtual testing allows identification and correction of potential pattern distortion issues before physical manufacturing, thereby improving pattern reproduction precision without changing the lithography wavelength.
2Measurement precision
If multiple 3-D resist profiles for different process conditions are generated and combined to create 3-D process variation band profiles, then the ability to visualize and correct lithographic process variations improves, but the computational complexity and processing time increase
Solution Approach 1:
The patent applies segmentation by dividing the lithographic process into multiple discrete process conditions (focus variations, dose variations, mask bias variations). Each condition is simulated separately to generate individual 3-D resist profiles, which are then combined to create the comprehensive 3-D process variation band profile. This segmented approach allows systematic analysis of each process parameter's impact while managing computational complexity through structured decomposition.
3Productivity
If 3-D process variation band profiles are generated to identify and correct pattern distortion issues, then the yield of semiconductor devices improves by reducing fabrication errors, but the time required for process optimization and mask fabrication increases
Solution Approach 1:
The patent applies copying by creating virtual 3-D representations of the lithographic process through computational simulations. Instead of physically testing every possible process condition and measuring resulting patterns, the system generates 3-D resist profiles that copy and represent the expected outcomes of different process conditions. This virtual copying allows rapid iteration and optimization of process parameters and mask designs, improving device yield while reducing the physical time required for fabrication testing.
Data Source
AI summary
In one embodiment, a method of manufacturing a semiconductor device includes using a processor to generate a first three dimensional (3-D) resist profile for a first process condition using an layout mask of a target structure. The method further includes using a processor to generate a second 3-D resist profile for a second process condition using the layout mask. The first process condition includes a plurality of process variables, and the second process condition includes different values of the plurality of process variables than the first process condition. The method includes generating a 3-D process variable (PV) band profile by combining the first 3-D resist profile with the second 3-D resist profile and displaying a 3-D image of the 3-D PV band profile on a display.