3D Resistance Change Memory Array With Conductive Pillars
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Solution Overview
Problem
Current non-volatile memory devices, such as flash memory, face challenges in increasing the degree of integration, particularly in next-generation technologies like ReRAM, which lack specific plans for enhanced integration.
Innovation Solution
A resistance change memory device array with a three-dimensional structure is developed, featuring conductive pillars and resistance change material layers between data lines, along with a selection device, to increase integration density and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional flash memory or early ReRAM structures are used, then device simplicity is maintained, but integration density remains low
Solution Approach 1:
The patent transitions from planar 2D memory cell layouts to a 3D vertical structure where conductive pillars extend upward from the substrate, with resistance change material layers deposited on pillar sidewalls and data lines positioned at multiple levels. This dimensional transition enables multiple memory cells to share common conductive pillars and data lines, dramatically increasing integration density while maintaining manufacturability through sequential layer deposition processes
2Quantity of substance
If data lines are positioned close together to increase density, then integration density improves, but leakage current between adjacent lines increases
Solution Approach 1:
The patent implements a nested structure where resistance change material layers are deposited conformally on the sidewalls of conductive pillars, creating vertically stacked memory cells that share common data lines. This nesting approach allows adjacent data lines to be positioned closely together while the vertical stacking and shared architecture reduce the effective parasitic coupling between lines, minimizing leakage current while maximizing density
3Productivity
If selection devices are added to enable selective programming, then data storage efficiency improves, but device complexity increases
Solution Approach 1:
The patent designs the conductive pillars to serve multiple functions: they act as word lines for selecting rows of memory cells, as common electrodes for resistance change operations, and as structural supports for vertically stacked cells. This multi-functionality eliminates the need for separate selection transistors at each cell location, achieving selective programming capability while maintaining relatively simple device structure and enabling high integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for higher integration density and efficient data storage by selectively programming, reading, and erasing data through voltage applications, minimizing leakage currents and improving overall device performance.
Implementation Method 1
resistance change material layer positioned between a sidewall of the conductive pillar and a sidewall of the data line adjacent to the sidewall of the conductive pillar
Data Source
AI summary
Provided are a resistance change memory device with a three-dimensional structure, a resistance change memory device array, an electronic product, and a manufacturing method therefor. The device array includes a plurality of first directional data lines which are arranged on a substrate in parallel. A conductive pillar is positioned between sidewalls of the first directional data lines, which face each other. A resistance change material film is positioned between the sidewall of the conductive pillar and the sidewall of the data lines that are adjacent to the sidewall of the conductive pillar.