3D Resistive Memory Device Block Selection Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current nonvolatile memory devices face challenges in achieving high integration and efficient data storage due to limitations in their three-dimensional resistive memory cell arrangements and control mechanisms.
Innovation Solution
A nonvolatile memory device with a three-dimensionally arranged resistive memory cell structure, utilizing local word lines and bit lines connected to global lines through selection units, and a block select circuit to manage memory blocks and banks, allowing for efficient data access and storage operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a three-dimensional structure to improve integration, then integration density is improved, but leakage current increases
Solution Approach 1:
The memory device is divided into multiple memory blocks, each with independent local word lines and local bit lines. This segmentation allows selective activation of only the required memory block and its associated lines, isolating potential leakage paths and preventing leakage current from affecting the entire array, thereby maintaining high integration density while controlling leakage.
Solution Approach 2:
Local word line selection units and local bit line selection units are introduced as intermediary components between the global word lines/bit lines and the memory cells. These selection units act as switches that can isolate inactive memory blocks, preventing leakage current from propagating through the entire three-dimensional structure while maintaining the high integration benefits of the 3D arrangement.
2Productivity
If local word lines and bit lines are connected to global lines through selection units to enable efficient data access, then data access efficiency is improved, but device complexity increases
Solution Approach 1:
The selection units are segmented into local word line selection units and local bit line selection units, each responsible for specific local lines within a memory block. This segmentation distributes the control complexity across multiple independent units rather than requiring a single complex control mechanism, enabling efficient data access while managing device complexity through modular design.
Solution Approach 2:
The patent introduces a hierarchical control structure with global word lines/bit lines at one level and local word lines/bit lines at another level, adding a dimensional aspect to the line organization. This multi-level hierarchical arrangement enables efficient data access by allowing selective activation of specific local lines within global line groups, while the structured hierarchy helps manage the overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces leakage current, enables high integration, and facilitates efficient read and write operations across memory cells, enhancing the overall performance of the memory device.
Implementation Method 1
Materials constituting the next generation semiconductor memory devices have different resistances according to current or voltage, and maintain their resistance even when a power supply is interrupted
Data Source
AI summary
A nonvolatile memory device includes resistive memory devices in a three-dimensional structure. A block select circuit generates a block select signal for selecting a memory block. In response to the block select signal, local word line selection units connected to each memory block connect global word lines connected to a word line decoder and local word lines, and local bit line selection units connected to each memory block connect global bit lines connected to a sense amplifier and local bit lines. Each memory block includes local word lines which extend in a first direction and are stacked in a second direction perpendicular to the first direction on a second plane perpendicular to a first plane. Local bit lines extend in the second direction to cross local word lines. Memory cells are formed at cross-points where local word lines and local bit lines cross one another.