3D Resistive Memory Stack Architecture for High Density Storage
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Solution Overview
Problem
Current semiconductor memory devices face limitations in increasing memory capacity due to high manufacturing costs associated with pattern miniaturization and limited capacity enhancement through multi-level cell techniques, necessitating innovative approaches to enhance integration density.
Innovation Solution
A three-dimensional semiconductor device design featuring a substrate with doped regions, bit lines, vertical electrodes, and a stack of horizontal electrodes, including selection lines and word lines, which are electrically separated to control memory patterns, allowing for increased integration density and efficient data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pattern miniaturization technique is used to increase memory capacity, then memory capacity is improved, but manufacturing cost increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking architecture. Multiple memory cells are stacked vertically along the channel region, with bit lines extending in first directions and word lines in second directions intersecting the bit lines. This vertical stacking enables increased memory capacity without requiring further miniaturization of individual cell patterns, thereby avoiding the associated manufacturing cost increases.
2Quantity of substance
If multi-level cell technique is used to increase memory capacity, then memory capacity is improved, but the capacity increase is limited to the number of bits per cell
Solution Approach 1:
The memory cell is segmented into distinct functional components arranged in three dimensions: vertical electrodes forming bit line plugs, horizontal electrodes forming word lines, and selection lines. Multiple memory cells are segmented and stacked vertically, with each cell containing memory patterns between the electrodes. This segmentation allows for scalable capacity increase through vertical stacking rather than increasing bits per cell, reducing the complexity associated with multi-level cell structures.
3Quantity of substance
If 3D-IC technique is combined with pattern miniaturization and MLC techniques, then memory capacity is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent merges the selection transistor gate electrode with the selection line structure, where the selection line extends over the channel region and serves as the gate electrode for the selection transistor. The bit line plug serves as the vertical electrode, and memory patterns are positioned between the bit line plug and word lines. This merging of functions into a unified three-dimensional structure achieves high memory capacity without the need for separate complex structures for each function, thereby reducing overall device complexity compared to combining multiple techniques.
Data Source
AI summary
Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.