3D RRAM Device with Shared Electrode for High Density
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Solution Overview
Problem
Current flash memory devices face challenges in scaling with critical dimensions less than 30 nm, including program/erase voltages, access speed, and reliability, which traditional three-dimensional floating gate memory devices are unable to adequately address.
Innovation Solution
The development of novel three-dimensional RRAM devices with a configuration of multiple bit levels, each comprising a first and second electrode with a variable resistance material, and a common electrode positioned between them, allowing for incremental changes in resistance through applied electric pulses without damaging the material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional three-dimensional floating gate memory devices are used for scaling, then memory device density can be increased, but program/erase voltages, access speed, and reliability deteriorate at critical dimensions less than 30 nm
Solution Approach 1:
The patent transitions from floating gate memory to RRAM technology, fundamentally changing the physical parameter used for data storage from charge trapping in a floating gate to resistance states in a variable resistance material layer. This parameter change enables continued scaling below 30 nm while maintaining reliability and performance characteristics that deteriorate in traditional floating gate devices.
Solution Approach 2:
The patent replaces the mechanical/physical structure of a stacked gate with floating gate electrode with an electric field-based RRAM cell structure consisting of two electrodes and a variable resistance material layer. This substitution eliminates the complex multi-layer gate structure and enables simpler scaling while improving access speed and voltage characteristics.
2Quantity of substance
If RRAM devices are configured with multiple bit levels and common electrodes, then bit density increases, but device structure complexity increases
Solution Approach 1:
The patent merges multiple RRAM bit levels by sharing a common electrode structure. Instead of providing separate electrode structures for each bit level, the invention combines multiple bit levels that share common electrodes, thereby increasing bit density while controlling the growth of structural complexity through resource sharing.
Solution Approach 2:
The common electrode serves multiple functions across different bit levels simultaneously. A single electrode structure is used universally for multiple bit levels, enabling the same physical component to participate in multiple memory cell operations, which increases storage capacity without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances bit densities and reduces the cost per bit of memory devices by enabling efficient data storage and retrieval in a scalable and reliable manner.
Implementation Method 1
The electric field strength or electric current density from the pulse, or pulses, is sufficient to switch the physical state of the materials so as to modify the properties of the material and establish a highly localized conductive filament (CF) in the variable resistance material.
Data Source
AI summary
Disclosed herein are various embodiments of novel three dimensional RRAM devices, and various methods of making such devices. In one example, a device disclosed herein includes a first electrode for a first bit line comprising a variable resistance material, a second electrode for a second bit line comprising a variable resistance material and a third electrode positioned between the variable resistance material of the first bit line and the variable resistance material of the second bit line.