3D Sealing Ring Structure for Stable Chip Perimeter Protection
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Solution Overview
Problem
Existing semiconductor seal rings are unable to provide adequate protection to chips due to their poor stability and smaller interception area, which fails to meet the increasing protection requirements as semiconductor device sizes decrease.
Innovation Solution
A semiconductor structure is manufactured with a sealing ring structure comprising multiple stacked subportions and a functional structure, both integrated into a first dielectric layer on the peripheral and chip regions of the substrate, enhancing stability and interception area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing seal ring structures are used, then the chip perimeter is protected, but the interception area is insufficient and stability is poor
Solution Approach 1:
The seal ring structure is divided into multiple subportions (first subportion, second subportion, third subportion) stacked in sequence, each contributing to the overall interception area. This segmentation allows the seal ring to achieve greater total interception area and improved stability without requiring a single large-scale structure that would be difficult to manufacture.
Solution Approach 2:
The seal ring transitions from a conventional two-dimensional planar structure to a three-dimensional stacked structure by arranging multiple subportions vertically. This dimensional change significantly increases the interception area while maintaining compatibility with existing chip manufacturing processes and enhancing structural stability.
2Productivity
If semiconductor device sizes decrease, then device integration increases, but the requirements for chip protection become more stringent
Solution Approach 1:
The multiple subportions of the seal ring are nested stacked in sequence, with each subportion contained within the vertical space of the overall structure. This nesting approach maximizes the use of three-dimensional space to achieve increased interception area and stability without increasing the lateral footprint, thereby maintaining high device integration density while meeting enhanced protection requirements.
Data Source
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AI summary
Embodiments of the present application relate to a semiconductor structure and a manufacturing method therefor, comprising: a substrate, the substrate comprising a peripheral region and a chip region; a first dielectric layer, located on the peripheral region and the chip region of the substrate; and a protective structure and a functional structure, located in the first dielectric layer of the peripheral region and the chip region, respectively. The protective structure comprises a first sub-portion, a second sub-portion, and a third sub-portion that are sequentially stacked. The functional structure comprises a fourth sub-portion and a fifth sub-portion that are sequentially stacked. The total height of the first sub-portion, the second sub-portion, and the third sub-portion is equal to the total height of the fourth sub-portion and the fifth sub-portion.