3D Memory Select Layer Isolation for Reliable High-Stack Integration
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Solution Overview
Problem
The operational reliability of three-dimensional semiconductor memory devices decreases as the number of stacked memory cells increases, due to challenges in maintaining effective integration and reliability.
Innovation Solution
A semiconductor memory device design that includes a source structure, stacked conductive layers, select conductive layers, insulating layers, slit structures, and a separation insulating structure, which are strategically arranged to enhance operational reliability by controlling the separation and insulation between conductive elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked memory cells is increased to improve the degree of integration, then the area occupied by memory cells per unit area is reduced, but the operational reliability of the three-dimensional semiconductor memory device decreases
Solution Approach 1:
The select conductive layer is divided into multiple separated regions by insulating structures, creating distinct segments that are electrically isolated from each other. This segmentation prevents electrical interference and short circuits between adjacent select regions, thereby maintaining operational reliability while allowing increased stacking density
Solution Approach 2:
Insulating structures are introduced as intermediary elements between adjacent select conductive regions. These intermediary insulating structures act as barriers that prevent direct electrical contact between neighboring conductive regions, enabling higher integration without compromising reliability
2Productivity
If the number of stacked memory cells is increased to improve the degree of integration, then the area occupied by memory cells per unit area is reduced, but pattern failure and fume discharge issues occur during manufacturing
Solution Approach 1:
The continuous select conductive layer is segmented into discrete regions by insulating structures. This segmentation simplifies the manufacturing process by allowing independent processing of each segment, reducing pattern failure rates and improving manufacturing precision during the formation of stacked memory cells
Solution Approach 2:
Insulating structures are formed in advance before the select conductive layer is deposited. This preliminary action defines the boundaries of select regions beforehand, guiding subsequent deposition processes and preventing fume discharge issues by controlling material placement in predetermined zones
Data Source
AI summary
Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a source structure, a stacked conductive layer that overlaps with the source structure, a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer, a stacked insulating layer disposed between the first and second select conductive layers and the stacked conductive layer, and a separation insulating structure provided between the first select conductive layer and the second select conductive layer.