3D Semiconductor Device Alignment and Testing
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Solution Overview
Problem
The development of true three-dimensional integrated circuits (3D ICs) faces challenges in yield and reliability due to complex architectures and alignment issues, particularly in deep submicron process generations, where existing testing techniques are not adequately effective.
Innovation Solution
The implementation of a 3D semiconductor device with monocrystalline layers and programmable interconnects, where transistors are aligned with less than 200 nm error, enabling the use of Look-Up-Table logic cells and programmable interconnects for improved alignment and testing, and incorporating redundancy and repair mechanisms for enhanced reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If Through Silicon Via technology is used to bond multiple layers of silicon to form true 3D IC, then three-dimensional integration is achieved, but alignment precision deteriorates due to complex architectures and alignment issues
Solution Approach 1:
The patent introduces an intermediary alignment layer or reference structure between the bonded silicon layers that serves as a mediator for alignment. This intermediary element allows for precise alignment registration during the bonding process, resolving the alignment precision deterioration caused by direct Through Silicon Via bonding of complex 3D IC architectures.
2Adaptability or versatility
If complex architectures are implemented in 3D IC, then device functionality is improved, but yield deteriorates due to yield and reliability difficulties
Solution Approach 1:
The patent segments the complex 3D IC architecture into modular functional blocks or standardized interface layers. This segmentation allows for independent fabrication, testing, and bonding of smaller units, thereby improving overall yield by isolating defects to specific segments rather than compromising the entire complex structure.
Solution Approach 2:
The patent employs parameter changes in the bonding process, such as adjusting bonding temperature, pressure, or time parameters, to optimize the bonding of complex 3D IC architectures. By carefully controlling these parameters, the patent achieves reliable bonding while maintaining the functionality of complex architectures, thus improving yield without sacrificing device versatility.
3Extent of automation
If existing testing techniques are applied to 3D IC, then testing capability is maintained, but measurement precision deteriorates due to inadequate effectiveness
Solution Approach 1:
The patent extends testing capabilities into the vertical dimension by implementing through-silicon via testing and interlayer connection verification specific to 3D IC architectures. This dimensional extension of testing allows for precise measurement of alignment and connectivity in the vertical stacking direction, thereby improving measurement precision for 3D IC-specific parameters while maintaining automated testing capability.
Data Source
AI summary
A 3D semiconductor device including: a first layer including a first monocrystalline layer, the first layer including first logic cells; a second layer including a monocrystalline semiconductor layer, the second layer overlying the first layer, the second layer including second transistors, where the logic cells include a Look-Up-Table logic cell, and where the second transistors are aligned to the first logic cells with less than 200 nm alignment error.