3D Semiconductor Device With Attic Level Logic For Yield Repair
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Solution Overview
Problem
The development of true three-dimensional integrated circuits (3D ICs) faces challenges in yield and reliability due to complex architectures and the need for new manufacturing techniques, particularly in deep submicron process generations, where existing testing methods are not adequately effective.
Innovation Solution
The solution involves a semiconductor device with multiple transistor layers and metal interconnects, where the programming circuitry is placed in an 'Attic' level above the functional circuitry, using Through Silicon Vias for bonding, and employing antifuse-based programmable logic elements for flexible interconnects and redundancy to enhance testing and repair capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Through Silicon Via technology is used to bond multiple transistor layers to form true 3D ICs, then device functionality and integration density are improved, but manufacturing complexity and alignment precision requirements increase significantly
Solution Approach 1:
The patent segments the 3D IC manufacturing process into distinct layers (first transistor layer, second transistor layer, Attic level) that can be fabricated and tested independently before final assembly. This segmentation allows each layer to be optimized and validated separately, reducing the cumulative alignment errors that would otherwise propagate through the entire stack.
Solution Approach 2:
The patent implements preliminary testing and validation of each transistor layer before bonding to the next layer. By performing functional tests and identifying defects early in the manufacturing process, the system prevents compounding alignment and functional issues, allowing for corrective actions before final assembly.
2Productivity
If complex logic circuits are implemented in deep submicron process generations, then device capability and integration density are improved, but yield and reliability deteriorate due to manufacturing variations
Solution Approach 1:
The patent incorporates redundant logic circuits and antifuse-based programmable elements that can compensate for manufacturing defects. By designing in built-in redundancy before manufacturing, the system creates a buffer against yield losses from deep submicron process variations, allowing defective circuits to be replaced by functional equivalents.
Solution Approach 2:
The patent uses antifuse elements that can be programmed after manufacturing to change the electrical parameters and connectivity of the circuit. This post-fabrication programmability allows the system to adapt to actual manufacturing variations by reconfiguring connections to avoid defective transistors or interconnects, thereby maintaining reliability despite process variations.
3Difficulty of detecting and measuring
If existing testing methods are applied to true 3D ICs, then some defects can be detected, but testing effectiveness is insufficient due to architectural complexity and lack of appropriate test access
Solution Approach 1:
The patent introduces Attic level circuitry as an intermediary testing layer that provides specialized test access points and control logic between the external tester and the embedded logic circuits. This intermediary layer enables sophisticated testing schemes including built-in self-test (BIST) capabilities and facilitates defect detection in deep submicron circuits where direct testing is ineffective.
Solution Approach 2:
The patent implements built-in self-test (BIST) capabilities within the logic circuits themselves, allowing the circuits to test their own functionality without requiring complex external testing equipment. This self-service approach enables continuous monitoring and detection of defects that would be difficult to detect with conventional external testing methods.
4Quantity of substance
If programming circuitry is integrated at the same level as functional circuitry, then device density is improved, but routing congestion and design complexity increase
Solution Approach 1:
The patent places programming circuitry in the Attic level, which is a separate vertical dimension above the functional logic circuits. This dimensional separation allows programming and functional circuits to coexist without competing for the same routing resources, eliminating routing congestion while maintaining high device density through efficient vertical stacking.
Data Source
AI summary
A three dimensional semiconductor device is described with two transistor layers overlaid. The first transistor layer comprises a plurality of flip-flops each having an input and an output, wherein the inputs are selectively coupleable to the second transistor layer.