3D Semiconductor Structure With Backside Interconnect for Low Leakage

The invention moves critical dimensions from the lateral plane to the vertical stacking direction. Instead of requiring ever-finer lateral patterning, the patent achieves higher integration by stacking multiple active layers vertically, where the critical dimensions are determined by vertical epitaxial growth and deposition processes rather than lateral lithography, thereby reducing manufacturing precision requirements for pattern formation.

The patent employs nested structures where gate electrodes wrap around vertically-stacked active layers in a conformal manner. This nesting approach allows multiple functional layers to be integrated in a compact vertical footprint, achieving high integration without requiring extremely fine lateral patterning, as the structures are formed through sequential deposition and growth processes.

The patent introduces vertical stacking of active layers with wrap-around gate electrodes, creating three-dimensional structures that provide superior gate control and operating characteristics. While the vertical stacking increases structural complexity, it enables enhanced performance through better electrostatic control and higher drive current density that cannot be achieved with planar structures.

The patent combines multiple active layers and gate electrodes into a single vertically-integrated transistor structure. This merging of multiple components into one stacked unit achieves improved operating characteristics through collective operation, where the combined structure provides higher current drive and better scaling behavior than individual planar transistors, justifying the increased structural complexity.