3D Semiconductor Device Oxide-to-Oxide Bonding Alignment
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Solution Overview
Problem
Current 3D semiconductor chip stacking technologies face challenges such as high-temperature processing requirements for transistors, which damage lower wiring layers, and limited connectivity due to misalignment and size constraints of contacts between wafers, resulting in low connectivity between layers.
Innovation Solution
The development of 3D semiconductor devices with horizontally oriented transistors and oxide-to-oxide bonding, using single crystal layers and alignment marks to enable self-aligned processing and high-density connectivity, and employing techniques like ion-cut layer transfer and replacement gates to maintain low processing temperatures and precise alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature processing (>700°C) is used to construct transistors in 3D stacked chips, then transistor performance and density improve, but the bottom wiring layer gets damaged
Solution Approach 1:
The patent divides the chip construction into separate stages: bottom wiring layer is constructed first at low temperature, then the top transistor layer is constructed at high temperature on a separate wafer, and finally the two layers are bonded together. This segmentation allows each layer to be processed at its optimal temperature without affecting the other.
Solution Approach 2:
The bottom wiring layer is constructed in advance at low temperature before the top transistor layer is added. This preliminary construction allows the wiring layer to be established and protected before exposure to high-temperature processing that would damage it.
2Device complexity
If wafer bonding is used to connect stacked layers, then 3D integration is achieved, but alignment issues and thermal expansion differences cause misalignment and limit connectivity density
Solution Approach 1:
The patent introduces an intermediary bonding layer between the top and bottom wafers that compensates for misalignment. This bonding layer acts as a mediator that absorbs alignment errors and thermal expansion differences, allowing high-density connectivity to be achieved despite bonding imperfections.
Solution Approach 2:
The patent changes the bonding parameters by using a bonding layer with specific material properties that tolerate misalignment. By adjusting the bonding layer thickness, material composition, and bonding temperature, the system achieves high alignment precision despite wafer bowing and thermal expansion issues.
3Reliability
If contact size is increased to ensure alignment tolerance during wafer bonding, then alignment robustness improves, but the number of connections between layers decreases
Solution Approach 1:
The patent implements a nested structure where multiple connectivity functions are integrated within a single contact structure. The contact includes a landing pad, through-silicon via, and bonding interface nested together, allowing small contact footprints to achieve robust alignment tolerance through the nested configuration rather than increasing individual contact size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the construction of 3D semiconductor devices with high-density connections and improved transistor performance while maintaining low processing temperatures, addressing the limitations of existing 3D stacking technologies.
Implementation Method 1
the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds
Data Source
AI summary
A method for producing a 3D memory device, the method comprising: providing a first level comprising a single crystal layer; forming at least one second level above said first level; performing a first etch step comprising etching holes within said second level; forming at least one third level above said at least one second level; performing a second etch step comprising etching holes within said third level; performing additional processing steps to form a plurality of first memory cells within said second level and a plurality of second memory cells within said third level, wherein each of said first memory cells comprise one first transistor, wherein each of said second memory cells comprise one second transistor, wherein at least one of said first or second transistors has a channel, a source and a drain having the same doping type, and wherein said forming at least one third level comprises forming a window within said third level to allow lithography alignment through said third level to an alignment mark underneath.