3D Semiconductor Memory Layout for Dense Cell Isolation
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Solution Overview
Problem
The integration density of two-dimensional (2D) semiconductor devices is limited by the high cost and complexity of forming fine patterns, necessitating the development of three-dimensional (3D) semiconductor memory devices to enhance reliability and integration density.
Innovation Solution
The design incorporates a horizontal structure on a substrate with sequentially stacked horizontal patterns, a stack structure of electrodes, and a separation structure that intersects both, allowing for increased integration density and improved reliability through a vertical arrangement of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional (2D) or planar semiconductor devices are used to achieve high integration density, then manufacturing costs increase due to the need for extremely high-priced apparatuses to form fine patterns, but transitioning to three-dimensional (3D) structures introduces increased device complexity
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional vertical structures by stacking multiple horizontal patterns (first horizontal pattern, second horizontal pattern) and electrodes vertically. This dimensional change enables higher integration density without requiring extremely fine pattern formation apparatuses, as the stacking approach uses more conventional fabrication processes to achieve greater functional density.
Solution Approach 2:
The device is segmented into distinct functional layers including substrate, first horizontal pattern, second horizontal pattern, stack structure with multiple electrodes, vertical patterns, and separation structures. This segmentation allows each layer to be formed using separate fabrication steps with more relaxed precision requirements compared to forming all features in a single planar layer, thereby reducing manufacturing costs while maintaining high integration density.
2Reliability
If the separation structure is positioned to intersect both the stack structure and horizontal structure, then reliability is improved through better isolation, but the manufacturing process becomes more complex
Solution Approach 1:
The separation structure is formed to extend through the substrate and intersect both the horizontal structure and stack structure in advance, establishing proper isolation between different device regions before subsequent fabrication steps. This preliminary positioning of the separation structure ensures reliable electrical isolation and structural definition, preventing interference between adjacent memory cells and improving overall device reliability while using standard fabrication sequencing.
Data Source
AI summary
3D semiconductor memory devices may include a horizontal structure that may be on an upper surface of a substrate and may include first and second horizontal patterns sequentially stacked on the upper surface of the substrate, a stack structure including electrodes stacked on the horizontal structure, a vertical pattern extending through the electrodes and connected to the first horizontal pattern, and a separation structure intersecting the stack structure and the horizontal structure and protruding into the upper surface of the substrate. A lowermost electrode may have first inner sidewalls facing each other with the separation structure interposed therebetween. The second horizontal pattern may have second inner sidewalls facing each other with the separation structure interposed therebetween. A maximum distance between the first inner sidewalls in the first direction may be less than a maximum distance between the second inner sidewalls in the first direction.