3D Semiconductor Channel Structure With Perpendicular Transistor Paths
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Solution Overview
Problem
The increasing demand for high-performance semiconductor devices with high integration density and multifunctionality poses challenges in achieving efficient operation due to the reduction in size of planar metal oxide semiconductor FETs, necessitating the development of three-dimensional structure channels.
Innovation Solution
A semiconductor device with a plurality of channel layers spaced apart on an active region of a substrate, surrounded by gate structures, and featuring source/drain regions and contact plugs to enhance integration density and operational efficiency, including a vertical semiconductor layer with a gate structure surrounding a portion of its lateral surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar metal oxide semiconductor FETs are reduced in size to increase integration density, then integration density is improved, but operational properties deteriorate
Solution Approach 1:
The patent transitions from planar (2D) channel structures to three-dimensional (3D) vertical channel structures. The channel extends vertically through multiple layers with gate structures wrapping around it, enabling increased integration density while maintaining operational properties by utilizing the vertical dimension for current flow rather than reducing horizontal dimensions.
Solution Approach 2:
The patent employs nested gate structures where first gate structures and second gate structures are positioned at different vertical levels, with the second gate structure surrounding the vertical region of the semiconductor layer. This nested arrangement allows multiple gating functions within a compact footprint, improving both integration density and operational control.
2Reliability
If three-dimensional vertical channel structures are implemented to maintain operational properties, then operational efficiency is improved, but device complexity increases
Solution Approach 1:
The patent divides the transistor structure into segmented components: multiple channel layers stacked vertically, separate first and second gate structures at different levels, and distinct source/drain regions. This segmentation allows each component to be optimized independently while working together to achieve efficient operation with controllable complexity.
Solution Approach 2:
The gate structures serve multiple functions: the first gate structure controls the channel at one vertical level while the second gate structure controls the vertical region, enabling independent optimization of different channel sections. This multi-functionality allows a single device structure to achieve complex operational characteristics without proportionally increasing overall device complexity.
Data Source
AI summary
A semiconductor device includes a plurality of channel layers disposed on an active region of a substrate and spaced apart from each other in a first direction, a first gate structure surrounding the plurality of channel layers, first source/drain regions disposed on the active region on both lateral sides of the first gate structure and contacting the plurality of channel layers and spaced apart from each other in a second direction, an element isolation layer disposed on an upper portion of the first gate structure, a semiconductor layer disposed on the element isolation layer and having a vertical region extending in the first direction and including second source/drain regions spaced apart from each other in the first direction, and a second gate structure disposed to surround a portion of the vertical region. The semiconductor device further includes first to fourth contact plugs.