3D Semiconductor Device with Charge Blocking Patterns
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Solution Overview
Problem
Three-dimensional non-volatile memory devices face issues with data retention due to charge leakage between stacked memory cells, insufficient cell current, and breakdown voltage problems, primarily caused by the thinness of the vertical channel layer and charge trapping layers.
Innovation Solution
A semiconductor device design featuring alternately stacked conductive and insulating layers, with a channel layer passing through them, and first charge blocking patterns formed by oxidizing a silicon source layer to reduce data storage layer thickness and increase channel layer thickness, thereby enhancing data retention and cell current, and establishing breakdown voltage between gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the vertical channel layer is made thinner to increase integration density, then the number of memory cells per area increases, but the cell current becomes insufficient
Solution Approach 1:
The patent introduces a charge blocking layer with different material properties (oxidized silicon) at specific locations (between data storage layers and conductive layers) to locally enhance charge confinement. This allows the channel layer to remain thin for high density while the localized charge blocking structures prevent charge leakage, enabling sufficient cell current without increasing channel thickness
Solution Approach 2:
The patent uses a composite structure combining silicon source layer and oxidized silicon charge blocking layer. The silicon source layer provides the channel function while the oxidized charge blocking layer provides charge confinement. This composite approach enables the thin channel to achieve both high density and sufficient current through the combined properties of the materials
2Reliability
If the data storage layer thickness is reduced to improve charge confinement, then charge leakage between memory cells decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces a charge blocking layer as an intermediary structure between the data storage layer and conductive layer. This intermediate layer acts as a buffer that enhances charge confinement without requiring extreme precision in the data storage layer thickness, as the charge blocking layer provides the primary confinement function
Solution Approach 2:
The charge blocking layer is formed before final device operation, pre-establishing the charge confinement mechanism. The oxidation of the silicon source layer creates the charge blocking structures in advance, ensuring proper charge confinement is established before the device begins operation, reducing the need for post-manufacturing adjustments
3Device complexity
If insulating layers are made thinner to reduce device complexity, then manufacturing steps are simplified, but breakdown voltage between gate electrodes cannot be established
Solution Approach 1:
The patent applies local quality enhancement by introducing charge blocking layers at specific critical interfaces (between data storage layers and conductive layers) rather than uniformly thickening all insulating layers. This localized approach maintains overall device simplicity while establishing breakdown voltage at the specific locations where charge confinement is needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves data retention, increases cell current, and ensures breakdown voltage, leading to enhanced performance and manufacturing ease in three-dimensional memory devices.
Implementation Method 1
forming a first charge blocking layer by oxidizing the first silicon source layer
Data Source
AI summary
The present disclosure may provide a semiconductor device with a low manufacturing degree of difficulty and an enhanced performance. The device may include conductive layers and insulating layers, alternately stacked, each of the insulating layers being thinner than each of the conductive layers; a channel layer passing through the conductive layers and the insulating layers; a data storage layer surrounding a side-wall of the channel layer; and first charge blocking patterns, each of the first charge blocking patterns interposed between the conductive layers and the insulating layers and between the data storage layer and the conductive layers.