3D Semiconductor Devices With Copper To Copper Wafer Bonding
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Solution Overview
Problem
The increasing cost of mask sets for semiconductor manufacturing and the limitations of Through-Silicon-Via (TSV) technology in achieving high vertical connectivity in 3D Integrated Circuits (ICs) hinder the development of efficient and cost-effective 3D IC devices, particularly due to the large size of TSVs which restricts the number of connections that can be made.
Innovation Solution
The use of layer transfer techniques, such as SmartCut and wafer bonding, to create 3D semiconductor devices with multiple layers of mono-crystalline silicon, enabling the construction of 3D ICs with improved vertical connectivity and reduced development costs by eliminating the need for antifuse programming logic and utilizing custom masks, thereby enhancing interconnect density and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Through-Silicon-Via (TSV) technology is used to achieve vertical connectivity in 3D ICs, then interconnect functionality is provided, but the large size of TSVs restricts the number of connections that can be made
Solution Approach 1:
The patent transitions from planar 2D interconnect architecture to three-dimensional stacked architecture, enabling vertical connectivity through multiple stacking levels. This dimensional change allows interconnects to extend in the vertical direction, providing additional connection pathways without consuming lateral chip area, thereby resolving the contradiction between connectivity and connection density.
Solution Approach 2:
The patent implements nested interconnect structures where multiple interconnect layers are stacked vertically within the same lateral footprint. Each stacking level contains interconnects that are nested within the vertical space of previous levels, enabling high-density connections by utilizing the third dimension (vertical space) rather than requiring additional lateral area.
2Ease of manufacture
If mask set cost is reduced by using standard masks instead of custom masks, then manufacturing cost decreases, but antifuse programming logic is required which adds device complexity
Solution Approach 1:
The patent extracts and removes the antifuse programming logic from the device architecture by implementing a fuseless programmable interconnect system. This extraction eliminates the need for complex antifuse structures and programming circuits, thereby reducing device complexity while enabling the use of standard masks for manufacturing, which reduces manufacturing cost.
Solution Approach 2:
The patent employs a fuseless programmable interconnect approach that uses simple, manufacturable structures instead of expensive and complex antifuse elements. This substitution with simpler, more manufacturable components reduces both device complexity and manufacturing cost, allowing standard masks to be used effectively.
3Adaptability or versatility
If layer transfer techniques are used to create 3D semiconductor devices, then vertical connectivity and interconnect density are improved, but manufacturing process complexity increases
Solution Approach 1:
The patent implements preliminary formation of interconnect structures and device layers on separate wafers before stacking. By preparing interconnects, contacts, and device layers in advance on individual wafers using standard processes, and then assembling them through bonding, the patent achieves complex 3D structures without requiring complex in-situ manufacturing processes, thereby reducing manufacturing process complexity.
Solution Approach 2:
The patent segments the manufacturing process into separate stages: forming device layers on one wafer, forming interconnect structures on another wafer, and then assembling them through bonding. This segmentation allows each component to be manufactured using simpler, optimized processes rather than requiring a single complex integrated process, thereby reducing overall manufacturing process complexity while achieving high vertical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a significant increase in vertical connectivity and reduces development costs, enabling more efficient and powerful 3D ICs by using custom masks to replace antifuse functions and leveraging layer transfer methods for improved interconnect density and power management.
Implementation Method 1
layer transfer techniques, such as SmartCut
Implementation Method 2
wafer bonding
Data Source
AI summary
A 3D integrated circuit, the circuit including: a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors, where the second wafer is bonded face-to-face on top of the first wafer, where the bonded includes copper to copper bonding, and where the second crystalline substrate has been thinned to a thickness of less than 5 micro-meters.