3D Semiconductor Device with Single Crystal Silicon and Cu Pillar Interconnects
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Solution Overview
Problem
Current 3D Integrated Circuit (IC) technologies face challenges in achieving high transistor performance and density due to limitations in Through-Silicon Via (TSV) density, alignment issues, and the need for high-temperature processing, which affects the reliability of interconnects and transistor performance.
Innovation Solution
The development of a 3D semiconductor device with a layered structure using single crystal silicon, where transistors with single crystal channels are stacked with precise alignment and connected via vias through the silicon layer, allowing for high-density interconnections and reduced temperature processing, enabling improved transistor performance and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Through-Silicon Via (TSV) technology is used to connect stacked wafers, then 3D integration is achieved, but TSV density is limited due to large landing pads requirements and alignment issues
Solution Approach 1:
The patent segments the connection path into multiple components: Cu pillars formed in first via holes, a second wafer bonded to the first wafer, and second via holes penetrating through the second wafer. This segmentation allows each component to be optimized independently, enabling higher density connections without requiring large landing pads for alignment tolerance.
Solution Approach 2:
The patent transitions from planar 2D interconnects to 3D vertical interconnects by stacking wafers and forming vertical Cu pillars and vias. This dimensional change enables significantly higher connection density by utilizing the vertical dimension, overcoming the density limitations of traditional planar TSV approaches.
2Ease of manufacture
If high-temperature processing is used to form TSVs, then via formation is achieved, but interconnect reliability and transistor performance deteriorate
Solution Approach 1:
The patent changes the temperature parameter from high-temperature TSV formation to low-temperature Cu pillar formation. Cu pillars are formed at lower temperatures than traditional TSVs, and the subsequent bonding and via formation processes are also conducted at controlled temperatures that preserve interconnect reliability while achieving the necessary via formation capability.
3Productivity
If device scaling is continued to improve performance and reduce cost, then device speed increases and area decreases, but interconnection wiring dominates performance and power
Solution Approach 1:
The patent addresses the interconnect bottleneck by moving from 2D planar wiring to 3D vertical wiring with Cu pillars and stacked wafers. This dimensional change shortens interconnect paths significantly, reducing both signal propagation delay (improving device speed) and power consumption associated with long interconnect wires.
4Quantity of substance
If TSV density is increased to improve interconnect capability, then connection density improves, but landing pad size and processing complexity increase
Solution Approach 1:
The patent segments the interconnection structure into discrete Cu pillars in first via holes, bonded wafer interfaces, and second via holes through the second wafer. This segmentation eliminates the need for large landing pads, as connections are made through precisely positioned pillars and vias. The modular structure simplifies processing while enabling high interconnection density.
Data Source
AI summary
A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where the via includes contact with at least one of the plurality of transistors.