3D Semiconductor Device with Direct Oxide Bonding
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and limited flexibility, particularly in constructing commercially viable logic families with diverse products, and they struggle with reducing inter-chip interconnects, which dominate IC performance and power consumption.
Innovation Solution
The development of a 3D IC technology using Through-Silicon-Via (TSV) connections, combined with a re-programmable antifuse and layer transfer techniques, allows for the creation of configurable logic devices with reduced mask costs and increased flexibility, enabling the construction of devices with various logic, memory, I/O, and analog functions, and utilizing repeating logic tiles connected via TSV for modular systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If current semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is limited
Solution Approach 1:
The patent segments the semiconductor fabrication process into modular components: standard front-end processing that can be reused across multiple products, and configurable logic blocks that provide flexibility. This segmentation allows different logic families to be constructed from the same base process, reducing mask-set costs while maintaining adaptability.
Solution Approach 2:
The patent implements universal logic tiles and repeating circuit blocks that can be configured through software to create different logic functions. This multi-functionality allows a single fabrication process to produce diverse logic families (CMOS, bipolar, BiCMOS) without requiring separate mask sets for each product type.
2Use of energy by moving object
If inter-chip interconnects are reduced in size, then IC performance and power efficiency improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar 2D interconnects to 3D vertical interconnects using Through-Silicon Vias (TSVs). This dimensional change allows interconnects to pass through the substrate vertically, reducing the lateral footprint and enabling denser routing while maintaining manufacturable dimensions through established TSV fabrication techniques.
Solution Approach 2:
The patent implements nested interconnect structures where multiple metal layers and TSVs are stacked vertically within the substrate thickness. This nesting approach packs more interconnect pathways into the same lateral area, reducing the overall chip size and power consumption while using standard fabrication precision for each individual layer.
3Productivity
If TSV connections are implemented, then inter-chip interconnects are reduced, but device complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-configuring logic tiles and circuit blocks during standard front-end processing, before the final product-specific customization. TSV patterns and interconnect structures are established in advance using standard processes, reducing the complexity of later customization steps while achieving high interconnect density.
Solution Approach 2:
The patent uses repeating logic tiles and standardized circuit blocks that can be copied and instantiated multiple times across the chip. These standardized units with integrated TSV connections reduce fabrication complexity by using the same proven processes repeatedly, while achieving high productivity through dense interconnect routing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the cost of manufacturing multiple mask sets, enhances flexibility in semiconductor device fabrication, and decreases the size and number of interconnects, thereby improving IC performance and power efficiency by enabling dense connections smaller than one micron in size.
Implementation Method 1
wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds
Data Source
AI summary
A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.