3D Semiconductor Dummy Patterns for Plasma Arcing Control
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Solution Overview
Problem
Conventional 3D semiconductor devices experience defects and electrical charge accumulation during deep trench etching, leading to arcing effects that damage the device due to the large area of conductive layers exposed to plasma, which increases the risk of electrical charge accumulation at weak points.
Innovation Solution
A 3D semiconductor device design featuring isolated dummy patterns around the array pattern, where multilayers are divided into separate blocks or islands to reduce the capacity for electrical charge storage, thereby minimizing the arcing effect by distributing the trenches and dummy islands in a net-like, concentric, or all-around-pads pattern to prevent charge accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the multi-layers extend to the big-ring region to cover the array pattern, then the structural completeness is improved, but the electrical charge accumulation and arcing effect worsen
Solution Approach 1:
The patent divides the continuous multi-layer structure into isolated dummy islands separated by deep trenches. This segmentation breaks the large continuous conductive area into smaller isolated regions, reducing the total capacity for electrical charge accumulation while maintaining structural coverage over the array pattern.
Solution Approach 2:
The patent applies different structural configurations to different regions: the dummy islands are strategically positioned in the big-ring region with specific patterns (net-like, concentric, or all-around-pads) to locally address charge accumulation problems where they occur most severely, while maintaining appropriate coverage elsewhere.
2Area of stationary object
If the big-ring region area is increased to provide better coverage, then the structural protection is improved, but the arcing effect worsens due to more electrical charge accumulation
Solution Approach 1:
The patent segments the extended multi-layer structure into isolated dummy islands separated by deep trenches. This allows the structure to maintain large coverage area in the big-ring region while preventing continuous charge accumulation paths, thereby maintaining reliability despite extended coverage.
Solution Approach 2:
The deep trenches act as intermediary elements that physically separate the conductive layers into isolated islands. These trenches serve as mediators that allow the structure to achieve both large coverage area and reduced charge accumulation by interrupting the continuous conductive path.
3Ease of manufacture
If the multi-layers are continuously stacked without isolation, then the manufacturing process is simplified, but the electrical charge accumulation at weak locations increases
Solution Approach 1:
The patent introduces segmentation of the continuous multi-layer structure into isolated dummy islands through deep trench separation. This segmentation can be integrated into existing manufacturing processes while effectively reducing charge accumulation at weak points by breaking continuous conductive paths.
Solution Approach 2:
The deep trenches are formed before final planarization and stacking completion, preliminarily establishing the isolated island structure. This preliminary action prevents charge accumulation issues before they occur during subsequent plasma processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces electrical charge accumulation and arcing effects, enhancing the electrical characteristics and reliability of the 3D semiconductor device by minimizing damage during the deep trench etching process.
Implementation Method 1
During the period of the deep trench etching, the electrical charges (symbol 'e' as shown in FIG. 1) from the plasma would be accumulated in the conductive layers
Implementation Method 2
which may have a high risk of arcing effect. The larger area of the big-ring region RBR is, the more serious arcing effect will be induced
Data Source
AI summary
A three-dimensional (3D) semiconductor device is provided, comprising: a substrate having a first area and a second area, and the second area adjacent to and surrounding the first area (i.e. active area), wherein an array pattern is formed in the first area; a stack structure having multi-layers formed above the substrate, and the multi-layers comprising active layers (ex: conductive layers) alternating with insulating layers above the substrate. The stack structure comprises first sub-stacks related to the array pattern in the first area; and second sub-stacks separately disposed in the second area, and the second sub-stacks configured as first dummy islands surrounding the first sub-stacks of the array pattern.