3D Semiconductor Electrode Structure for High-Integration Reliability
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Solution Overview
Problem
The challenge in semiconductor devices is to increase integration while overcoming the limitations of expensive process equipment required for fine pattern formation in two-dimensional or planar devices.
Innovation Solution
The semiconductor device incorporates a peripheral circuit structure on a substrate, with a horizontal layer, electrode structures having pads in a stepwise shape, a planarization insulating layer, contact plugs, penetration vias, and vertical conductive structures between the electrode structure and the penetration via.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional or planar semiconductor devices use fine pattern forming technology to increase integration, then integration is improved, but expensive process equipment is required
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensionally arranged memory cells. The bit lines, word lines, and charge storage structures are arranged in multiple vertical layers, enabling higher integration without requiring finer lateral patterning. This vertical stacking approach achieves increased capacity while avoiding the need for extremely expensive fine pattern forming equipment.
2Productivity
If three-dimensionally arranged memory cells are implemented to increase integration, then integration is improved, but device deformation and cracks may occur
Solution Approach 1:
The three-dimensional memory structure is divided into multiple discrete horizontal layers separated by insulating layers. Each layer can be independently formed and controlled, allowing stress to be distributed across multiple interfaces rather than concentrated in a single continuous structure. This segmentation reduces the risk of deformation and crack propagation through the entire device.
Solution Approach 2:
Insulating layers are introduced between the conductive layers (bit lines, word lines, charge storage structures) to act as mechanical buffers and stress distributors. These intermediary layers prevent direct stress transfer between adjacent conductive structures, reducing the likelihood of deformation and crack formation while maintaining the three-dimensional integrated architecture.
Data Source
AI summary
A semiconductor device including a peripheral circuit structure on a substrate, a horizontal layer on the peripheral circuit structure, an electrode structure including electrodes on the horizontal layer, the electrodes including pads arranged in a stepwise shape, a planarization insulating layer covering the pads, a contact plug penetrating the planarization insulating layer and coupled to one of the pads, a penetration via penetrating the planarization insulating layer and coupled to the peripheral circuit structure, and a vertical conductive structure between the electrode structure and the penetration via may be provided. The vertical conductive structure may have a bottom surface located at a level that is higher than a top surface of the horizontal layer and is lower than a bottom end of the contact plug.