3D Semiconductor Device Hybrid Bonding and Thinning
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Solution Overview
Problem
In 3D stacked integrated circuits, the degradation of wire performance with 'scaling' and the challenge of heat removal due to increased power density and thermal resistance hinder the efficiency and reliability of the devices.
Innovation Solution
A method involving the growth of an epitaxial layer on a silicon wafer, transferring and bonding it onto another wafer, thinning it to less than ten microns, and incorporating a shielding metal layer and a global power distribution network with higher conductivity to improve alignment and heat removal, while using hybrid bonding and optical annealing to repair lattice damage without damaging underlying metal interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional scaling is applied to reduce component sizes, then transistor performance and density improve, but wire performance degrades
Solution Approach 1:
The patent transitions from 2D planar scaling to 3D vertical stacking, where multiple transistor layers are stacked above each other. This dimensional change allows continued transistor density improvement without further reducing wire lengths in the lateral direction, thereby preventing wire performance degradation while achieving higher productivity.
2Loss of time
If 3D stacking is implemented to reduce wire lengths, then wiring delay decreases, but heat removal becomes more difficult due to increased power density and thermal resistance
Solution Approach 1:
The patent segments the heat removal function by introducing separate thermal management structures, including heat sinks attached to the bottom of the substrate and thermal vias penetrating through the substrate. This segmentation allows heat to be extracted from multiple locations and pathways, improving overall heat removal efficiency despite the 3D stacked configuration.
Solution Approach 2:
The patent introduces an intermediary thermal management system consisting of heat sinks, thermal interface materials, and thermal vias that act as mediators between the heat-generating 3D stacked transistors and the external environment. These intermediary structures facilitate efficient heat transfer while allowing the 3D stacking architecture to maintain low wiring delay.
3Reliability
If optical annealing is used to repair lattice damage, then underlying metal interconnects are protected from damage, but the process complexity increases
Solution Approach 1:
The patent replaces conventional thermal annealing (a mechanical/thermal process that heats the entire structure) with optical annealing using photon beams. This substitution allows selective heating of only the semiconductor layers requiring repair, while the underlying metal interconnects remain cool and undamaged. Although the optical process adds complexity, it enables precise spatial control that protects sensitive metal layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and reliability of 3D ICs by reducing wire misalignment and improving heat dissipation, maintaining the integrity of metal interconnects and reducing thermal resistance.
Implementation Method 1
performing growth of an epitaxial layer on top of said silicon layer, said epitaxial layer comprising non silicon atoms
Implementation Method 2
using hybrid bonding and optical annealing to repair lattice damage without damaging underlying metal interconnects
Data Source
AI summary
A method to form a 3D semiconductor device, the method including: providing a first level including first circuits, the first circuits including first transistors and first interconnection; preparing a second level including a silicon layer; forming second circuits over the second level, the second circuits including second transistors and second interconnection; transferring with bonding the second level on top of the first level; and then thinning the second level to a thickness of less than ten microns, where the bonding includes oxide to oxide bonds, and where the bonding includes metal to metal bonds.