3D Semiconductor Interconnect Structure for High-Density Patterning
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Solution Overview
Problem
The increasing demand for high performance, high speed, and multifunctionality in semiconductor devices necessitates finer patterns and higher integration densities, which poses challenges in manufacturing with fine widths and spacings.
Innovation Solution
A semiconductor device design incorporating a lower structure with a substrate and transistors, an intermediate structure featuring multiple insulating layers and interconnection structures, and an upper structure with data storage capabilities, including stopper layers and gap-fill insulating layers to support complex interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased to achieve higher performance, then functionality and speed are improved, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent divides the interconnection structure into multiple segments including lower interconnection structure, intermediate interconnection structure, and upper interconnection structure. Each segment is separated by intermediate insulating structures with multiple insulating layers, allowing independent formation and reducing overall manufacturing complexity while achieving high integration density
Solution Approach 2:
The patent introduces vertical dimensionality by stacking intermediate structures between lower and upper interconnection structures. This multi-layer vertical arrangement enables higher integration density by utilizing the third dimension (height) rather than only horizontal expansion, thereby increasing functionality without proportionally increasing planar manufacturing complexity
2Quantity of substance
If finer patterns are implemented to achieve higher integration density, then device capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The interconnection structures are segmented into distinct lower, intermediate, and upper portions with clear separations provided by intermediate insulating structures. This segmentation allows each patterned layer to be formed independently with standard precision requirements, avoiding the need to manufacture entire fine-pitch interconnection networks in a single high-precision step
Solution Approach 2:
Intermediate insulating structures act as intermediary elements between lower and upper interconnection structures. These intermediaries provide physical separation and isolation, allowing finer patterns to be formed in upper layers without directly constraining the manufacturing precision of lower layers, thereby reducing overall precision requirements while maintaining high integration density
3Adaptability or versatility
If multiple insulating layers are added to support complex interconnections, then flexibility and functionality are improved, but structural complexity increases
Solution Approach 1:
The insulating structure is segmented into multiple functional layers including first intermediate insulating layer, second intermediate insulating layer, and third intermediate insulating layer. Each layer serves specific functions (isolation, mechanical support, stress management) and can be independently optimized, providing interconnection flexibility without requiring a monolithic complex structure
Solution Approach 2:
The intermediate insulating structures serve multiple functions simultaneously: they provide electrical isolation between interconnection layers, mechanical support for fine-pitch patterns, stress management to reduce warpage, and structural templates for subsequent patterning. This multi-functionality reduces the need for additional dedicated structures, thereby increasing versatility without proportionally increasing structural complexity
Data Source
AI summary
Provided is a semiconductor device including: a lower structure including a substrate, and a lower transistor on the substrate; an intermediate structure on the lower structure; and an upper structure on the intermediate structure, the upper structure including an upper transistor and a data storage structure, wherein the intermediate structure includes: an intermediate interlayer insulating layer on the lower structure; an intermediate interconnection structure including an intermediate plug and an intermediate interconnection portion on the intermediate plug, wherein the intermediate plug penetrates the intermediate interlayer insulating layer; an intermediate stopper layer including an intermediate stopper horizontal portion on the intermediate interlayer insulating layer, and an intermediate stopper extension portion extending from the intermediate stopper horizontal portion and covering a side surface and an upper surface of the intermediate interconnection portion; and an intermediate gap-fill insulating layer on an external side surface of the intermediate stopper extension portion and on the intermediate stopper horizontal portion of the intermediate stopper layer.