3D Semiconductor Device With Multiple Isolation Layers
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and struggle with the large size of Through Silicon Vias (TSVs) that restrict the number of connections in 3D ICs.
Innovation Solution
The development of a 3D IC fabrication method using a re-programmable antifuse in conjunction with Through Silicon Via (TSV) to construct configurable logic, allowing for the creation of multiple layers with oxide-to-oxide and metal-to-metal bonds, enabling smaller, more efficient connections and reducing the need for multiple mask sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Through Silicon Vias (TSVs) are used to connect multiple layers in 3D ICs, then electrical connections between layers are achieved, but the large size of TSVs restricts the number of connections that can be made
Solution Approach 1:
The patent segments the connection structure by introducing multiple isolation layers between transistor layers, creating distinct bonding interfaces. This segmentation allows for more compact connection pathways and increases the density of connections that can be made without requiring large TSV structures.
Solution Approach 2:
The patent introduces a vertical dimension to the connection architecture by stacking isolation layers between transistor layers. This multi-layer isolation structure creates additional bonding surfaces and enables more connections to be made in the vertical dimension, effectively increasing connection density without enlarging the horizontal footprint of individual connections.
2Ease of manufacture
If conventional fabrication methods with multiple mask sets are used, then precise transistor structures can be formed, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent employs a universal fabrication approach where the same fabrication processes and equipment are used across multiple isolation layers and transistor layers. The isolation layers serve multiple functions: electrical isolation, mechanical support, and bonding interfaces. This multi-functionality reduces the need for specialized mask sets and processes for each layer type, thereby lowering manufacturing costs while maintaining precision through standardized processes.
Solution Approach 2:
The patent utilizes parameter changes in the isolation layer properties (such as oxide thickness, material composition, and bonding temperature) to achieve precise transistor structures without requiring additional mask sets. By carefully controlling these parameters, the same fabrication equipment can produce precise structures across multiple layers, reducing both cost and increasing flexibility.
3Reliability
If oxide-to-oxide and metal-to-metal bonds are used between layers, then bonding strength and electrical connectivity are improved, but the fabrication process becomes more complex
Solution Approach 1:
The patent merges the isolation function and bonding function into the same structural elements. The isolation layers are designed to serve as bonding interfaces, eliminating the need for separate bonding structures. This merging of functions maintains reliability through strong oxide-to-oxide and metal-to-metal bonds while simplifying the overall fabrication process by reducing the number of discrete components and steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, enhances flexibility in producing various logic, memory, and analog functions, and allows for a higher density of connections in 3D ICs, making 3D IC technology more applicable across different device applications.
Implementation Method 1
the bonded includes at least one oxide to oxide bond
Implementation Method 2
the bonded includes at least one metal to metal bond
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including single crystal first transistors, and a first metal layer, where the first level is overlaid by a first isolation layer; a second level including second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, where the third level is bonded to the second isolation layer, where the bonded includes at least one oxide to oxide bond, and where the bonded includes at least one metal to metal bond.