3D Semiconductor Device With Thin Isolation Layers
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Solution Overview
Problem
Current 3D Integrated Circuit (IC) technologies face challenges in achieving high transistor performance and density due to limitations in wafer alignment, TSV density, and the need for high-temperature processing, which affects the reliability of interconnects and increases costs.
Innovation Solution
The development of a 3D semiconductor device with multiple layers of single crystal transistors separated by thin isolation layers, utilizing a layer transfer process that allows for low-temperature bonding and cleaving, enabling high-density interconnects and efficient transistor construction without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Through Silicon Vias (TSV) are used to connect bonded wafers, then electrical connections between layers are achieved, but the density of interconnects is limited due to large landing pad requirements and misalignment issues
Solution Approach 1:
The patent transitions from planar 2D wafer bonding to 3D stacked architecture with vertical interconnects. By stacking multiple thin semiconductor layers vertically and using conductive vias through the stack, the invention achieves high interconnect density (millions per chip) compared to traditional TSV approaches. The vertical dimension enables compact routing and eliminates the need for large landing pads.
Solution Approach 2:
The invention changes the physical parameters of the interconnect structure by using smaller diameter vias (sub-micron scale) and reducing the spacing between interconnect elements. By optimizing via diameter, spacing, and depth, the patent achieves high-density interconnect arrays that overcome the limitations of conventional TSV technology.
2Area of stationary object
If thin semiconductor layers are used to increase interconnect density, then device area is reduced, but handling and processing becomes difficult and prone to yield loss
Solution Approach 1:
The patent introduces a carrier substrate as an intermediary that supports thin semiconductor layers during fabrication and handling. The carrier provides mechanical strength and handling convenience while allowing the thin active layers to be processed. After stacking, the carrier can be released, enabling the thin-layer 3D structure to function while having been easily manufactured.
3Strength
If conventional wafer bonding is used to stack layers, then structural integrity is achieved, but the process requires high temperatures and complex alignment procedures
Solution Approach 1:
The patent changes the bonding parameters by using low-temperature bonding processes (below the temperature threshold that would damage interconnects). By optimizing bonding pressure, temperature, and time parameters, the invention achieves sufficient structural integrity for 3D stacking without requiring high-temperature conventional bonding procedures.
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including single crystal first transistors, where the first level is overlaid by a first isolation layer; a second level including single crystal second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, and where the first isolation layer and the second isolation layer are separated by a distance of less than four microns.