3D Semiconductor Device With Junction-Less Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D integrated circuit technologies face challenges in constructing high-density connections between layers with minimal processing temperatures, particularly in forming transistors and memory cells without junctions, and achieving efficient layer transfer and alignment for advanced memory architectures.
Innovation Solution
The development of junction-less transistors and layer transfer techniques such as ion-cut, which allow for the construction of 3D stacked semiconductor chips with high-density connections by forming single-crystal silicon transistors atop wiring layers at low temperatures, using methods like hydrogen implantation and oxide-to-oxide bonding, and implementing monolithic 3D integration concepts for resistive and charge-trap memory architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 3D integrated circuit technologies are used to construct high-density connections between layers, then connection density is improved, but processing temperature requirements increase
Solution Approach 1:
The invention divides the transistor structure into distinct layers (first transistor layer, second transistor layer, third transistor layer) that can be formed and processed separately at low temperatures, then stacked together. This segmentation allows each layer to be optimized independently and avoids the need for high-temperature processing that would be required if all layers were formed monolithically.
Solution Approach 2:
The invention implements a nested structure where the second transistor layer is positioned within the projection area of the first transistor layer, and the third transistor layer is positioned within the projection area of the second transistor layer. This nested arrangement enables high-density vertical integration while maintaining low processing temperatures, as each nested layer can be formed independently using low-temperature processes.
2Temperature
If junction-less transistors are used to reduce processing temperature, then temperature is reduced, but manufacturing complexity increases
Solution Approach 1:
The invention employs self-aligned fabrication processes where the second transistor layer is automatically aligned to the first transistor layer through the overlay relationship, and the third transistor layer is automatically aligned to the second transistor layer. This self-alignment mechanism eliminates the need for complex external alignment procedures and reduces manufacturing complexity despite the multi-layer junction-less structure.
3Quantity of substance
If multiple layers of transistors are stacked to increase density, then connection density is improved, but alignment precision requirements increase
Solution Approach 1:
The invention establishes predetermined overlay relationships between transistor layers during the design and fabrication planning stage. The first, second, and third transistor layers are designed with specific geometric relationships that ensure proper alignment when stacked. This preliminary planning of overlay relationships simplifies the actual manufacturing alignment process and reduces precision requirements during fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the creation of high-density 3D integrated circuits with reduced processing temperatures, enabling efficient alignment and connection of transistors and memory cells, and facilitates the construction of advanced memory architectures with improved performance and density.
Implementation Method 1
using methods like hydrogen implantation and oxide-to-oxide bonding
Implementation Method 2
using methods like hydrogen implantation and oxide-to-oxide bonding
Data Source
AI summary
A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors overlaying the at least one first metal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell overlaying the memory peripheral circuits; and a second memory cell overlaying the first memory cell, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type.