3D Semiconductor Device with Junction-Less Transistors and TSV
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and existing 3D IC technologies are constrained by large Through Silicon Via (TSV) sizes, which restrict the number of connections that can be made.
Innovation Solution
The development of a 3D semiconductor device with a layered structure comprising logic circuits and memory cells using junction-less transistors, where the second transistors are aligned with less than 150 nm alignment error, and the integration of Through-Silicon-Via (TSV) technology to enable high-density connections, allowing for the construction of configurable logic, memory, and analog functions within a modular and re-programmable framework.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional semiconductor fabrication methods are used, then manufacturing processes are well-established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent segments the semiconductor fabrication process into multiple reusable template layers (first template layer, second template layer, third template layer) that can be independently designed and reused across different product families. This allows a single mask set to produce multiple logic families by recombining template layers, thereby reducing mask-set costs while maintaining manufacturing process stability
Solution Approach 2:
The patent creates universal template layers that can serve multiple functions across different logic families. The first template layer can be reused for both first logic family and second logic family devices, and the second template layer serves as a common intermediate structure. This multi-functionality reduces the total number of mask sets required while maintaining ease of manufacture
2Quantity of substance
If traditional 3D IC technology is used, then through silicon vias provide vertical connections, but TSV sizes are large which restricts the number of connections
Solution Approach 1:
The patent transitions from traditional planar 2D IC layout to 3D stacked architecture where logic circuits and memory cells are arranged in vertical layers. Multiple template layers are stacked vertically with interconnect structures connecting corresponding elements across layers, enabling significantly higher connection density without increasing lateral TSV dimensions
Solution Approach 2:
The patent implements a nested structure where third template layers are formed within or upon second template layers, and first template layers are integrated with subsequent layers. This nested arrangement maximizes the use of vertical space and allows multiple levels of interconnection within a compact volume, increasing the number of connections without proportionally increasing TSV size
Data Source
AI summary
A 3D semiconductor device including: a first level including logic circuits, the logic circuits include a plurality of first single crystal transistors and a first metal layer; a second level including a plurality of second transistors, where the second level includes memory cells including the plurality of second transistors; a second metal layer atop the second level; where the plurality of second transistors are junction-less transistors, where at least one of the plurality of second transistors includes polysilicon, where the memory cells are structured as a plurality of at least sixteen sub-arrays, where each of the sub-arrays is independently controlled, where at least one of the plurality of at least sixteen sub-arrays is at least partially atop at least one of the logic circuits, and where the at least one of the logic circuits is designed to control at least one of the plurality of at least sixteen sub-arrays.