3D Semiconductor Memory Cell Structure with External Selector Layer
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Solution Overview
Problem
Three-dimensional (3D) semiconductor devices with multi-layer stacked memory cell structures face reliability and electrical property issues due to heat accumulation and excessive heat generation, leading to reduced performance and increased power consumption.
Innovation Solution
A 3D semiconductor device structure featuring memory layers with interlayer insulation, memory cell structures arranged in arrays with selector and electrode layers, and a conductive layer connecting adjacent memory cells, where the selector layer is positioned externally to reduce heat generation and the conductive layer provides multiple current paths, thereby enhancing reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-layer stacked memory cell structures are used to increase storage capacity, then storage capacity is improved, but heat accumulation increases and reliability deteriorates
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to vertical 3D stacking architecture, where memory layers are stacked in the vertical direction above a common substrate. This dimensional change allows multiple memory cells to share common word lines and bit lines, increasing storage capacity while distributing heat generation across multiple layers for better thermal management.
Solution Approach 2:
The memory device is divided into multiple independent memory layers separated by interlayer insulation layers. Each memory layer contains memory cell structures with selector layers and electrode layers, allowing the device to be segmented into functional units that can operate independently and dissipate heat separately, improving overall reliability.
2Quantity of substance
If multi-layer stacked memory cell structures are used to increase storage capacity, then storage capacity is improved, but heat generation increases and power consumption increases
Solution Approach 1:
Common word lines and bit lines are shared across multiple memory layers, allowing a single set of conductors to address memory cells in different layers. This multi-functional approach increases storage capacity without proportionally increasing the number of conductors and associated power consumption, as the same lines serve multiple layers.
Solution Approach 2:
Multiple memory layers are combined into a single integrated structure with shared substrate, interlayer insulation, and common electrode layers. This merging allows the device to achieve higher storage capacity in a compact form factor while reducing the overall power consumption compared to implementing separate memory devices for each layer.
3Reliability
If selector layer is positioned internally in memory cell structure, then electrical connection is achieved, but heat generation increases and reliability decreases
Solution Approach 1:
The selector layer is extracted from the internal position within the memory cell structure and repositioned to the outer surface of the memory material layer. This extraction allows the selector layer to be thermally isolated from the heat-generating memory material, reducing heat generation and improving reliability while maintaining electrical connection functionality.
Data Source
AI summary
A three-dimensional semiconductor device includes a multi-layered stack structure with memory layers parallel to each other and separated by interlayer insulation layers; and memory cell structures formed at each memory layer by arranging in a multi-row and multi-column array. One memory cell structure includes a memory material layer; a selector layer formed at an outer surface of the memory material layer and connected to the memory material layer; a first electrode layer formed at an outer surface of the selector layer and electrically connected to the selector layer; and a second electrode layer formed at an inner surface of the memory material layer and connected to the memory material layer, wherein the second electrode layer penetrates the multi-layered stack structure. Each memory layer includes a conductive layer electrically connecting the first electrode layer and the conductive layer electrically connects the adjacent memory cell structures.