3D Semiconductor Memory Device Vertical Integration
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Solution Overview
Problem
Current two-dimensional semiconductor devices face limitations in integration due to the need for expensive process equipment for finer pattern formation, making it costly to increase integration density.
Innovation Solution
A three-dimensional semiconductor memory device is developed with a stack structure of electrode layers and insulating layers, featuring vertical semiconductor patterns and a gate insulating layer with a blocking insulating layer and charge storing patterns, allowing for increased integration without the need for expensive equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited due to area constraints and expensive fine pattern forming equipment requirements
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory structures. Multiple memory cell layers are stacked in the vertical direction, allowing integration density to increase without requiring proportionally finer lateral patterning. The stack structure includes alternating electrode layers and insulating layers extending vertically, with memory cells formed in each layer, effectively utilizing the third dimension to overcome area limitations.
Solution Approach 2:
The patent implements a nested structure where multiple memory cell layers are stacked within a single footprint area. Each memory cell layer contains electrode patterns, insulating layers, and semiconductor structures that are nested vertically. This nested arrangement allows multiple functional layers to occupy the same lateral space, significantly increasing integration density without requiring proportionally more expensive fine pattern equipment.
2Quantity of substance
If fine pattern forming technology is advanced to increase integration, then integration density improves, but manufacturing cost increases due to expensive process equipment
Solution Approach 1:
By stacking memory cells vertically in three dimensions, the patent achieves high integration density without requiring extremely fine lateral patterning. The vertical stacking allows multiple cell layers to be formed using relatively coarser lateral patterns, reducing dependence on expensive fine pattern forming equipment while maintaining high integration.
Solution Approach 2:
The memory device is segmented into multiple discrete memory cell layers stacked vertically. Each layer can be fabricated using standard patterning processes, and the layers are separated by insulating layers. This segmentation allows the use of less expensive patterning equipment for each individual layer while achieving high overall integration through the stacked configuration.
3Quantity of substance
If three-dimensional stacked structure is implemented, then integration density increases, but device complexity increases due to multiple layers and patterns
Solution Approach 1:
The patent employs universal repeating units for the memory cell layers, where each layer follows the same structural pattern of electrode layers, insulating layers, and semiconductor structures. This modular, repetitive design simplifies the fabrication process despite the increased number of layers, as the same patterning and deposition processes can be repeated for each layer rather than requiring unique complex processes for each.
Solution Approach 2:
The vertical stacking in the third dimension allows the device to achieve high integration without proportionally increasing lateral complexity. The repetitive vertical structure simplifies the overall design compared to attempting to achieve the same integration density through lateral expansion, which would require increasingly complex two-dimensional patterning.
Data Source
AI summary
Disclosed are a three-dimensional semiconductor memory device, an electronic system including the same, and a method of fabricating the same. The semiconductor memory device may include a stack structure including electrode layers and electrode interlayer insulating layers, which are alternately stacked on a substrate, vertical semiconductor penetrating the stack structure and placed adjacent to the substrate, and a gate insulating layer between the vertical semiconductor patterns and the stack structure. The gate insulating layer may include a blocking insulating layer adjacent to the stack structure, and charge storing patterns, which are spaced apart from the stack structure with the blocking insulating layer therebetween and are arranged along a surface of the blocking insulating layer. As a distance to the blocking insulating layer decreases, widths of the charge storing patterns may increase.