3D Semiconductor Memory Device With Dielectric Patterns
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Solution Overview
Problem
Conventional two-dimensional semiconductor devices face limitations in integration due to the expensive equipment required for fine pattern formation, leading to a need for three-dimensional semiconductor memory devices with improved stability and electric properties.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a substrate having a cell array region and an extension region, featuring a peripheral circuit structure, a stack structure of interlayer dielectric layers and gate electrodes, and contacts with protruding and vertical parts for electrical connection, along with dielectric patterns for structural support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional two-dimensional semiconductor devices are used, then manufacturing process is simpler, but integration is limited due to expensive equipment requirements for fine pattern formation
Solution Approach 1:
The patent transitions from conventional two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory structures. The stack structure comprises multiple interlayer dielectric layers and gate electrodes alternately stacked, creating vertical channels that extend through the stack. This dimensional change enables significantly higher integration density without requiring proportionally more expensive fine pattern formation equipment, as the vertical stacking approach naturally increases capacity rather than relying solely on reducing lateral feature sizes.
2Productivity
If three-dimensional vertically stacked structures are implemented, then integration capability is improved, but structural stability may be compromised
Solution Approach 1:
The stack structure is segmented into multiple alternating layers of interlayer dielectric material and gate electrodes. Each layer is formed separately and contributes to the overall structural integrity. The dielectric layers provide mechanical support and electrical isolation, while the gate electrodes provide structural framework. This segmentation into discrete, well-defined layers enhances the stability of the three-dimensional structure compared to attempting to form a monolithic vertical structure.
Solution Approach 2:
The stack structure employs composite construction with alternating dielectric and conductive materials. The interlayer dielectric layers and gate electrode layers are combined to create a composite structure that leverages the mechanical stability of dielectric materials and the structural integrity of metal or doped semiconductor gate electrodes. This composite approach ensures that the vertical stack maintains structural stability while achieving high integration capability.
3Reliability
If contacts penetrate through the stack structure, then electrical connection is achieved, but contact precision and alignment with gate electrodes become more difficult
Solution Approach 1:
The contacts are formed to penetrate through the stack structure at predetermined locations before final assembly and connection steps. The protruding parts of the contacts are positioned to contact the sidewalls of gate electrodes in advance, ensuring proper alignment and electrical connection. This preliminary formation of contacts with protruding portions that extend toward or contact gate electrode sidewalls simplifies the overall manufacturing process by establishing electrical connections early in the fabrication sequence, reducing the need for subsequent complex alignment operations.
Data Source
AI summary
Disclosed are three-dimensional semiconductor memory devices, electronic systems including the same, and methods of fabricating the same. The three-dimensional semiconductor memory device includes a substrate including a cell array region and an extension region, a peripheral circuit structure including peripheral transistors on the substrate, a stack structure including interlayer dielectric layers and gate electrodes that are alternately stacked on the peripheral circuit structure, contacts that penetrate the stack structure on the extension region and are electrically connected with the peripheral transistors and include a protruding part contacting a sidewall of one of the gate electrodes and a vertical part penetrating the stack structure, and dielectric patterns between the vertical part and respective sidewalls of the gate electrodes. Top and bottom surfaces of each of the dielectric patterns are respectively in contact with adjacent ones of the interlayer dielectric layers.