3D Semiconductor Memory Device Ferroelectric Thin Film Quenching
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Solution Overview
Problem
Current two-dimensional semiconductor devices face limitations in degree of integration due to expensive equipment requirements for pattern miniaturization, and there is a need for improved ferroelectric properties in three-dimensional semiconductor memory devices to enhance performance and integration.
Innovation Solution
A method for manufacturing a ferroelectric thin film with improved properties using a quenching-based process after heat treatment, involving the formation of a mold structure, channel holes, vertical channel structures, and gate electrodes, with a cooling rate of −180 degrees/sec to −90 degrees/sec, and using materials like HfOx and PZT for data storage patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional semiconductor devices use conventional pattern miniaturization techniques, then manufacturing precision is improved, but device complexity and manufacturing cost increase due to expensive equipment requirements
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked in the vertical direction, achieving higher integration density without requiring further miniaturization of individual cell patterns. This dimensional transition resolves the contradiction by improving integration capacity while avoiding the need for increasingly complex pattern miniaturization equipment.
Solution Approach 2:
The memory device is divided into multiple independent memory cells stacked vertically, with each cell containing separated functional components (word line, bit line, select transistors, and storage elements). This segmentation allows each cell to be independently formed through standardized processes, reducing overall device complexity while achieving high integration through vertical stacking.
2Reliability
If ferroelectric thin film is used in three-dimensional semiconductor memory devices, then residual polarization is improved, but manufacturing precision deteriorates due to difficulty in controlling crystal phase and orientation
Solution Approach 1:
The patent optimizes multiple process parameters including deposition temperature, oxygen partial pressure, deposition rate, and post-deposition annealing conditions to control the crystal phase and orientation of the ferroelectric thin film. By precisely controlling these parameters, the film achieves desired crystal structures (such as orthorhombic or tetragonal phases) with appropriate c-axis or r-axis orientations, thereby improving residual polarization while maintaining manufacturing precision.
Solution Approach 2:
The patent employs composite material structures, such as combining ferroelectric materials with specific buffer layers, electrode materials, or barrier layers. These composite structures help control crystal growth, stabilize desired phases, and improve film quality. The interaction between different materials in the composite structure enables precise control over crystal phase and orientation, resolving the manufacturing precision challenge.
3Reliability
If heat treatment process is applied to ferroelectric thin film, then coercive electric field is improved, but energy consumption increases
Solution Approach 1:
The patent combines the heat treatment process for improving coercive electric field with other necessary processing steps such as crystallization, phase transformation, or stress relief treatments. By merging multiple functions into a single heat treatment step, the process achieves multiple objectives simultaneously, reducing total energy consumption compared to performing separate treatments.
Solution Approach 2:
The heat treatment process is designed to serve multiple purposes: improving coercive electric field, controlling crystal phase, relieving internal stress, and stabilizing film structure. This multi-functional approach allows a single heat treatment step to achieve several objectives, thereby reducing overall energy consumption while maintaining reliability improvements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in a three-dimensional semiconductor memory device with enhanced residual polarization and coercive electric field values, improving the device's integration and reliability, suitable for multi-bit memory elements.
Implementation Method 1
performing a heat treatment process and a cooling process for the vertical channel structures, wherein the forming of the vertical channel structures includes: forming a data storage pattern configured to conformally cover an inner sidewall of each of the channel holes; and forming a vertical semiconductor pattern covering a sidewall of the data storage pattern, wherein the data storage pattern is formed of a ferroelectric thin film having a single-layer structure, wherein a cooling rate of the cooling process is −180 degrees/sec to −90 degrees/sec.
Implementation Method 2
the heat treatment process may include heating to a first temperature for a first time interval and maintaining the first temperature for a second time interval.
Data Source
AI summary
Disclosed is a method of manufacturing a three-dimensional semiconductor memory device including a ferroelectric thin film. The method includes forming a mold structure including interlayer dielectric layers and sacrificial layers alternately stacked on a substrate, forming channel holes penetrating the mold structure, forming vertical channel structures inside the channel holes, forming an isolation trench penetrating the mold structure and having a line shape extending in one direction, selectively removing the sacrificial layers exposed by the isolation trench, forming gate electrodes filling a space from which the sacrificial layers are removed, and performing a heat treatment process and a cooling process for the vertical channel structures.