3D Semiconductor Memory Device Modular Fabrication
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and existing 3D IC technologies are constrained by large Through Silicon Via (TSV) sizes, which restrict the number of connections that can be made.
Innovation Solution
The development of a 3D IC device fabrication method using a re-programmable antifuse in conjunction with Through Silicon Via (TSV) to create a configurable logic system, allowing for the construction of various logic, memory, I/O, and analog functions with repeating logic tiles and modular approaches, and utilizing layer transfer techniques to achieve high-density connections smaller than one micron in size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The fabrication process is divided into multiple reusable mask sets that can be combined in different sequences to produce different logic families. Instead of requiring a complete new mask set for each product, the process segments the patterning into modular stages that can be reconfigured through different assembly sequences, reducing mask-set costs while maintaining flexibility.
Solution Approach 2:
The fabrication methodology introduces dynamic reconfigurability where the same physical mask sets can be dynamically reassigned to different product configurations through varying process sequences and parameter adjustments. This allows a single mask set to serve multiple logic family requirements, enhancing adaptability without proportionally increasing manufacturing complexity.
2Productivity
If existing 3D IC technologies use Through Silicon Via (TSV), then connections are established, but TSV sizes are large which restricts the number of connections
Solution Approach 1:
The invention transitions from traditional vertical TSV connections to a combination of partial-depth vias and lateral connections within intermediate layers. By adding the lateral dimension to the connection architecture, the system achieves higher connection density without increasing vertical via size, effectively bypassing the TSV size limitation through dimensional expansion of the interconnect topology.
Solution Approach 2:
The interconnect structure implements nested layers of connections where smaller partial-depth vias are embedded within larger structural contexts, and lateral interconnects are nested within intermediate dielectric layers. This nested architecture allows multiple connection pathways to coexist in a compact volume, increasing the number of connections without proportionally increasing overall structure size.
Data Source
AI summary
A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and at least one metal layer, where the at least one metal layer interconnecting the first transistors; a plurality of first logic gates including the at least one metal layer interconnecting the first transistors; a plurality of second transistors atop the at least one metal layer; a plurality of third transistors atop the second transistors; a top metal layer atop the third transistors; and a memory array including wordlines, where the memory array includes at least four rows by four columns of memory mini arrays, where each of the mini arrays includes at least four rows by four columns of memory cells, and where each of the memory cells includes at least one of the second transistors or at least one of the third transistors.