3D Semiconductor Memory Device With Reconfigurable Logic And TSV Interconnects
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and limited flexibility, particularly in constructing commercially viable logic families with diverse products, and they struggle with integrating high-density connections in 3D ICs due to the large size of Through Silicon Vias (TSVs).
Innovation Solution
The development of a 3D IC technology using a re-programmable antifuse in conjunction with Through Silicon Via (TSV) to create configurable logic, allowing for the construction of devices with varying logic, memory, I/O, and analog functions, and enabling the use of repeating logic tiles with Through-Silicon-Via (TSV) connections that are less than one micron in size, thus enhancing interconnect density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is limited
Solution Approach 1:
The patent implements re-programmable antifuse technology that allows the semiconductor device to be reconfigured after manufacturing. This dynamic reprogrammability enables the same physical device to be adapted for different logic families and applications, resolving the contradiction between manufacturing efficiency and post-manufacturing flexibility.
Solution Approach 2:
The invention changes the electrical parameters of the antifuse structures through re-programming, transforming them from fixed-state connections to reconfigurable logic elements. This parameter change enables a single manufactured device to serve multiple logical functions, reducing mask-set costs while improving flexibility.
2Quantity of substance
If Through Silicon Via (TSV) connections are used in 3D ICs, then interconnect density is improved, but the large size of TSVs limits integration density
Solution Approach 1:
The patent transitions from planar 2D interconnects to three-dimensional TSV-based interconnects, adding a vertical dimension to the interconnect architecture. This dimensional change enables higher interconnect density by utilizing the third dimension, while the re-programmable logic layers above and below the TSVs maintain flexibility to manage the increased complexity.
Data Source
AI summary
A 3D semiconductor device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where a second metal layer is disposed atop the first metal layer; a plurality of logic gates including the first metal layer and first transistors; a plurality of second transistors disposed atop the second metal layer; a plurality of third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, where the memory array includes at least four memory mini arrays, where each of the mini arrays includes at least two rows by two columns of memory cells, where each memory cell includes one of the second transistors or one of the third transistors, and where one of the second transistors is self-aligned to one of the third transistors, being processed following a same lithography step.