3D Semiconductor Device With Oxide-to-Oxide Bonding and Optical Annealing
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Solution Overview
Problem
The semiconductor industry faces challenges in 3D stacked chip integration due to the degradation of wiring performance and high power consumption, limited connectivity between layers, and the need for high-temperature processing that damages lower-temperature wiring layers, leading to low connectivity and reliability issues.
Innovation Solution
The development of a 3D semiconductor device with a first silicon layer, isolation layer, and metal layers that allow for the construction of transistors and capacitors using single crystal silicon, enabling oxide-to-oxide bonding and high-density connectivity without degrading existing layers, and the use of optical annealing to repair defects and activate dopants at temperatures above 400°C without damaging underlying metal interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors are constructed using high-temperature processing (>700°C), then transistor performance and density improve, but lower-temperature wiring layers (<400°C) are damaged
Solution Approach 1:
The patent divides the semiconductor structure into separate crystalline layers at different temperature levels. Transistor layers are formed at high temperatures (>700°C) while wiring layers are formed at lower temperatures (<400°C), with isolation layers between them to prevent thermal damage. This segmentation allows each layer to be processed at its optimal temperature without affecting other layers.
Solution Approach 2:
The patent introduces isolation layers as intermediary structures between high-temperature transistor layers and low-temperature wiring layers. These isolation layers act as thermal barriers and mechanical separators, preventing the heat from damaging the wiring layers while allowing the transistors to be processed at high temperatures for optimal performance.
2Speed
If 3D stacking is implemented to reduce wire lengths, then wiring delay decreases, but connectivity between layers is limited
Solution Approach 1:
The patent transitions from 2D planar interconnects to 3D vertical interconnects by stacking multiple crystalline layers. Through-silicon vias (TSVs) and vertical contact structures enable connections between layers, reducing wire lengths and wiring delay while providing high-density connectivity in the vertical dimension.
Solution Approach 2:
The patent implements nested structures where multiple crystalline layers are stacked vertically with each layer containing transistors and interconnects. The layers are nested together with vertical vias passing through them, creating a compact 3D structure that achieves high connectivity density while minimizing wire lengths.
3Reliability
If contact size is increased to ensure alignment during wafer bonding, then bonding reliability improves, but contact density decreases
Solution Approach 1:
The patent performs preliminary alignment mark formation and bonding surface preparation before actual wafer bonding. Alignment marks are pre-formed on bonding surfaces, and bonding conditions are pre-optimized to enable precise alignment with smaller contact pads, thereby increasing contact density while maintaining bonding reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the construction of high-density 3D stacked semiconductor chips with improved connectivity and reliability, reducing thermal resistance and power consumption while maintaining the integrity of lower-layer components.
Implementation Method 1
wherein said isolation layer comprises an oxide to oxide bond surface
Implementation Method 2
the use of optical annealing to repair defects and activate dopants at temperatures above 400°C without damaging underlying metal interconnects
Data Source
AI summary
A semiconductor device, the device comprising: a first silicon layer comprising first single crystal silicon; an isolation layer disposed over said first silicon layer; a first metal layer disposed over said isolation layer; a second metal layer disposed over said first metal layer; a first level comprising a plurality of transistors, said first level disposed over said second metal layer, wherein said isolation layer comprises an oxide to oxide bond surface, wherein said plurality of transistors comprise a second single crystal silicon region; and a plurality of capacitors, wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.