3D Semiconductor Memory Device Vertical Integration

The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory structures. Multiple memory cell layers are stacked along the vertical direction, with each layer containing memory cells formed by intersecting word lines and bit lines. This dimensional change enables significantly higher integration density by utilizing the vertical space above the substrate rather than being constrained to a single plane.

The patent implements a hierarchical nesting structure where multiple memory cell layers are nested vertically above each other. Each memory cell layer contains transistors and storage elements that are nested within the three-dimensional structure. The word lines, bit lines, and select lines are arranged in nested configurations across multiple layers, with lower layers supporting upper layers, creating a compact nested architecture that maximizes integration density.

Instead of continuously reducing feature sizes in the two-dimensional plane, the patent achieves higher integration density by stacking multiple memory cell layers vertically. This approach shifts the integration challenge from lateral pattern scaling to vertical layer formation, allowing use of existing fine pattern forming technologies for lateral features while adding complexity only in the vertical stacking process.

The patent divides the memory device into multiple discrete memory cell layers, each with its own set of word lines, bit lines, and storage elements. This segmentation allows each layer to be formed using standard fabrication processes, and the layers are then combined through vertical stacking. The segmentation approach reduces the manufacturing precision requirements for individual layers compared to creating a single ultra-dense two-dimensional structure.

The patent implements three-dimensional vertically stacked memory structures where multiple memory cell layers are stacked along the vertical direction. Each layer contains memory cells formed by the intersection of word lines and bit lines, with select lines controlling access to specific layers. This vertical stacking achieves high integration density while maintaining relatively simple two-dimensional patterns within each layer.

The patent uses identical transistor structures and storage element designs across all memory cell layers, allowing the same fabrication processes to be repeated for each layer. The word lines, bit lines, and select lines serve universal functions across layers, with only their spatial positions differing. This universality simplifies the overall device complexity by reducing the number of unique structure types that must be manufactured.