3D Semiconductor Memory Integration Density via Vertical Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration density due to the high cost and complexity of fine pattern formation technologies, necessitating the development of three-dimensional semiconductor memory devices with increased integration density.
Innovation Solution
A three-dimensional semiconductor memory device design featuring vertically stacked semiconductor patterns with source/drain regions, a channel region, and word lines, where the gate insulating layer is interposed between the word lines and semiconductor patterns, and interlayered insulating layers are alternately stacked with semiconductor patterns, allowing for increased integration density without the need for expensive high-resolution equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory cells. The bit lines, word lines, and memory cells are arranged in multiple vertical layers, enabling increased integration density by utilizing the third dimension (vertical direction) rather than only the horizontal plane.
Solution Approach 2:
The patent implements a nested structure where multiple bit lines and word lines are stacked vertically, with memory cells formed at the intersections of these lines across different layers. The gate insulating layer is nested between the word lines and bit lines, creating a compact multi-layered configuration that maximizes space utilization.
2Reliability
If gate insulating layer is extended between source/drain regions, then interference between adjacent patterns is reduced, but manufacturing complexity increases
Solution Approach 1:
The gate insulating layer serves dual functions: it acts as the gate insulating layer between the word line and bit line channel regions, and simultaneously serves as an interlayered insulating layer extending between the source/drain regions of adjacent memory cells. This multi-functionality reduces the need for separate insulating layers, simplifying the fabrication process while maintaining reliability.
Solution Approach 2:
The patent merges the gate insulating layer and interlayered insulating layer into a single continuous insulating structure. The gate insulating layer is extended to also function as the interlayered insulating layer between adjacent memory cells, combining two insulating functions into one unified structure that reduces manufacturing steps.
Data Source
AI summary
A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.