3D Semiconductor Memory With Stacked Layers and Vertical Vias
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of integrating semiconductor memory devices into a three-dimensional form has not been adequately addressed, leading to inefficiencies in data storage and retrieval.
Innovation Solution
A semiconductor memory device is designed with a multi-layered structure comprising stacked memory layers, via-wirings, and gate electrodes, allowing for efficient electrical connections and data access through a complex network of transistors and capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a three-dimensional structure is adopted to increase integration, then data storage capacity is improved, but device complexity increases
Solution Approach 1:
The patent transitions from planar to three-dimensional memory architecture by stacking multiple memory layers (first memory layer, second memory layer, etc.) vertically. This dimensional change enables increased data storage capacity without proportionally increasing the footprint area, while the structured stacking pattern helps manage the resulting complexity through systematic organization.
Solution Approach 2:
The memory device is divided into multiple discrete memory layers, each containing its own set of transistors and capacitors. This segmentation allows independent optimization and control of each layer, reducing the overall complexity management by breaking down the three-dimensional structure into manageable modular units that can be fabricated and tested separately.
2Quantity of substance
If multiple memory layers are stacked to enhance storage capacity, then data storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary sacrificial layers (first sacrificial layer, second sacrificial layer) that are deposited and patterned before the actual memory structures are formed. These sacrificial layers serve as temporary molds or supports during fabrication, enabling precise positioning of vias and interconnect structures in the final three-dimensional memory architecture without requiring extremely tight tolerances in subsequent processing steps.
Solution Approach 2:
The sacrificial layers act as intermediary structures during manufacturing, facilitating the formation of vertical vias and interlayer connections. These intermediary layers simplify the manufacturing process by providing a convenient reference structure for aligning and connecting different memory layers, thereby reducing the direct precision requirements between adjacent memory structures.
3Speed
If via-wirings are used to connect stacked layers, then electrical connection efficiency is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple functions into the via-wiring structures: electrical interconnection between layers, signal routing, and structural support for layer alignment. By merging these functions into a single integrated element rather than separate components, the patent achieves efficient electrical connections between stacked memory layers while minimizing the additional complexity that would arise from separate interconnect and alignment structures.
Data Source
AI summary
A semiconductor memory device includes: a substrate; a first via-wiring extending in a first direction; first semiconductor layers electrically connected to the first via-wiring; memory portions electrically connected to the first semiconductor layers; first gate electrodes opposed to the first semiconductor layers; first wirings extending in a second direction, and electrically connected to the first gate electrodes; second semiconductor layers electrically connected to the first wirings; second gate electrodes opposed to the plurality of second semiconductor layers; a second via-wiring extending in the first direction and electrically connected to the second gate electrodes; and a second wiring extending in the first direction, electrically connected to the second semiconductor layers, and arranged with the second semiconductor layers in a third direction.