3D Semiconductor Device With Modular Logic Dies And TSV Interconnects
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and limited flexibility, particularly in constructing commercially viable logic families with diverse products, and they struggle with reducing inter-chip interconnects, which dominate IC performance and power consumption.
Innovation Solution
The development of a 3D IC technology using Through-Silicon-Via (TSV) connections and a modular approach with configurable logic dies, memory dies, and analog dies, allowing for mixing and matching different process-manufactured dies, and incorporating antifuse programmable interconnects for efficient power distribution and reduced congestion in circuit interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional semiconductor fabrication methods are used, then manufacturing process is established, but mask-set costs are high and flexibility is limited
Solution Approach 1:
The patent segments the semiconductor fabrication process into modular components: separate logic die, memory die, and analog die that can be independently manufactured and then combined. This segmentation allows different logic families to be produced by simply changing which pre-manufactured dies are combined, eliminating the need for new mask sets for each logic family variation.
Solution Approach 2:
The patent transitions from planar 2D integration to 3D vertical integration by stacking multiple dies vertically and connecting them through Through-Silicon-Vias. This dimensional change enables greater design flexibility and logic family variety without requiring additional lithography mask sets, as the variety is achieved through vertical stacking combinations rather than horizontal layout variations.
2Reliability
If traditional IC interconnection methods are used, then circuit connections are established, but inter-chip interconnects dominate power consumption and reduce performance
Solution Approach 1:
The patent merges multiple functional dies (logic, memory, analog) into a single integrated 3D structure, eliminating the need for separate inter-chip connections. By combining these functions within one stacked device, the interconnect paths are shortened and integrated, reducing both power consumption and signal degradation associated with traditional inter-chip bonding.
Solution Approach 2:
The patent uses vertical stacking with Through-Silicon-Vias to create short, direct vertical interconnect paths instead of long horizontal inter-chip traces. This dimensional change reduces interconnect length by orders of magnitude, thereby reducing RC delays and power consumption while improving signal integrity and overall IC performance.
3Productivity
If more TSV connections are used to increase connectivity, then more connections per area are achieved, but the size and number of TSVs increases
Solution Approach 1:
The patent applies local quality by concentrating TSV connections strategically at specific locations where vertical interconnects are most needed, rather than uniformly distributing them across the entire die area. This allows high connection density in critical regions while minimizing overall TSV area consumption.
Solution Approach 2:
The patent implements nesting by placing multiple functional layers and interconnect structures within the vertical stack, where each layer shares common TSV infrastructure. This nested arrangement allows multiple connections to share the same vertical pathway, increasing effective connections per area without proportionally increasing total TSV area.
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer and first single crystal transistors; a first metal layer; a second metal layer disposed atop the first metal layer; second transistors disposed atop of the second metal layer; third transistors disposed atop of the second transistors, where at least one of the third transistors includes at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate, and where a distance from at least one of the third transistors to at least one of the first transistors is less than 2 microns.