3D Semiconductor Device Monocrystal Silicon Channel
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Solution Overview
Problem
As semiconductor devices shrink to sizes like 22 nm and 10 nm, the increased resistance in polysilicon channel regions leads to reduced induction efficiency, decreased induction intensity, and increased series resistance, affecting read current and read speed of memory arrays, potentially causing memory cell failure.
Innovation Solution
A 3-D semiconductor device with floating gates implanted in vertical channel sidewalls, using a gate electrode and floating gate coupling to control source-drain regions, featuring a channel layer, inter-layer insulating layers, gate stack structures, and source/drain configurations made from specific materials like monocrystal silicon and high-k dielectric layers to enhance induction efficiency and reduce source-drain resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If polysilicon channel regions are used in 3-D semiconductor devices at 22 nm and 10 nm scales, then device integration density is improved, but channel resistance increases significantly leading to reduced induction efficiency and increased series resistance
Solution Approach 1:
The patent changes the material parameter of the channel layer from polysilicon to monocrystal silicon, which fundamentally alters the electrical properties by reducing resistance and improving carrier mobility. This parameter change directly addresses the induction efficiency problem while maintaining the 3-D vertical channel structure that enables high integration density.
Solution Approach 2:
The patent employs a composite material structure combining monocrystal silicon channel layer with high-k dielectric materials (such as HfO2, Al2O3, TiO2) for the gate dielectric layer. This composite approach allows the monocrystal silicon to provide low resistance while the high-k dielectric provides strong gate control, together solving both the induction efficiency and density requirements.
2Volume of moving object
If device size is reduced to 22 nm and 10 nm modes, then memory cell density is improved, but series resistance increases and read current decreases
Solution Approach 1:
The patent changes the channel material from polysilicon to monocrystal silicon, which fundamentally improves carrier mobility and reduces series resistance. This parameter change enables the device to maintain high read current even at reduced 22 nm and 10 nm dimensions, as monocrystal silicon's superior electrical properties compensate for the smaller cross-sectional area.
Solution Approach 2:
The patent utilizes vertical 3-D channels extending perpendicular to the substrate surface, transitioning from planar 2-D to vertical 3-D architecture. This dimensional change allows the channel length to extend in the vertical direction while maintaining small footprint area, and the monocrystal silicon material ensures low resistance along this vertical path, maintaining read current despite reduced lateral dimensions.
3Ease of manufacture
If polysilicon channel regions are used, then manufacturing process compatibility is maintained, but induction intensity decreases and memory cell operation fails
Solution Approach 1:
The patent changes the channel material parameter from polysilicon to monocrystal silicon, which fundamentally improves the electrical properties for induction. While this requires modifications to the manufacturing process (such as using different deposition and crystallization techniques), the improved induction intensity and reliability are achieved, with the process changes being manageable within existing semiconductor fabrication capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the induction efficiency and strength of source-drain regions, reducing memory cell resistance and increasing read current and read speed of memory arrays.
Implementation Method 1
When a voltage is applied to the gates, the fringe field of the gate will enable a plurality of source-drain regions to be formed on the sidewalls of pillar-shaped channels
Implementation Method 2
a gate dielectric layer (such as high-k dielectric materials) are deposited on the side walls of the projecting structures
Data Source
AI summary
A 3-D semiconductor device comprising a plurality of memory cells and a plurality of selection transistors, each of said plurality of memory cells comprises: a channel layer, distributed along a direction perpendicular to the substrate surface; a plurality of inter-layer insulating layers and a plurality of gate stack structures, alternately laminating along the sidewall of the channel layer; a plurality of floating gates, located between the plurality of inter-layer insulating layers and the sidewall of the channel layer; a plurality of drains, located at the top of the channel layer; and a plurality of sources, located in the said substrate between two adjacent memory cells of the said plurality of memory cells.