3D Multilayer Semiconductor Structure With Monocrystalline Channels
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Solution Overview
Problem
Existing 3D integrated circuits face challenges with wire performance degradation due to scaling, which affects IC performance, functionality, and power consumption, and current 3D memory structures using poly-silicon channels suffer from higher cell-to-cell performance variations and lower drive than monocrystalline channels.
Innovation Solution
The development of multilayer semiconductor devices with monocrystalline channels, utilizing epitaxial growth of SiGe and single crystal silicon layers, and oxide-to-oxide bonding to form self-aligned transistors, allowing for efficient connection and control of memory cells across multiple levels with shared lithography steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If poly-silicon channels are used in 3D memory structures, then manufacturing is simplified, but cell-to-cell performance variations increase and drive capability decreases
Solution Approach 1:
The patent changes the material parameter from poly-silicon to monocrystalline silicon for the channel region. This fundamental material parameter change resolves the contradiction by providing both manufacturing feasibility through epitaxial growth and superior electrical performance with reduced cell-to-cell variation and enhanced drive capability compared to poly-silicon channels
2Productivity
If component sizes are scaled down, then transistor performance and density improve, but wire performance degrades
Solution Approach 1:
The patent transitions from 2D planar scaling to 3D vertical stacking architecture. By stacking multiple transistor layers vertically, the invention achieves higher transistor density without further lateral scaling, thereby avoiding the wire performance degradation that occurs with continued miniaturization of interconnect dimensions
3Ease of operation
If 3D stacking is implemented, then wire lengths are reduced and wiring delay is kept low, but device complexity increases
Solution Approach 1:
The patent segments the 3D memory structure into multiple discrete transistor layers stacked vertically, with each layer containing complete memory cells. This segmentation allows independent processing and integration of individual layers, managing the complexity of 3D stacking through modular layer construction while achieving reduced wire lengths and low wiring delay
4Reliability
If monocrystalline channels are used, then drive capability and performance uniformity improve, but manufacturing complexity increases
Solution Approach 1:
The patent replaces the conventional mechanical/polymer-based poly-silicon deposition process with epitaxial growth of monocrystalline silicon layers. This substitution achieves superior performance uniformity and drive capability through controlled crystalline growth, while the epitaxial process itself provides a manufacturable pathway despite increased process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces construction costs and improves device performance by aligning transistors and reducing wire lengths, enabling independent control of memory cells and efficient interconnects in a 3D IC structure.
Implementation Method 1
performing an epitaxial growth of a SiGe layer on top of the second single crystal silicon layer
Implementation Method 2
performing an epitaxial growth of a third single crystal silicon layer on top of the SiGe layer
Implementation Method 3
performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones
Data Source
AI summary
Methods of making a 3D multilayer semiconductor device, including: providing a first substrate including a first level, the first level including a first single crystal silicon layer (SCSL); providing a second substrate including a second level, the second level including a second SCSL; performing an epitaxial growth of a SiGe layer on top of the second SCSL; performing an epitaxial growth of a third SCSL on top of the SiGe layer, the third SCSL has an average thickness of less than 2,000 nm; forming second transistors each including a single crystal channel, where forming the second transistors includes growth of a second SiGe layer on top of the third SCSL; forming many metal layers interconnecting the second transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second SCSL.