3D Semiconductor Device Monocrystalline Channels
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Solution Overview
Problem
Current 3D memory technologies face challenges with wire performance and power consumption due to the degradation of interconnects as transistors are scaled down, and existing 3D memory structures often use poly-silicon for active memory cell channels, which results in higher cell-to-cell performance variations and lower drive capabilities compared to monocrystalline channels.
Innovation Solution
The development of multilayer 3D memory structures using monocrystalline channels formed through alternative methods beyond ion cut and successive layer transfers, allowing for oxide-to-oxide bonding between levels and incorporating programmable logic circuits and differential signaling, enabling efficient memory cell construction with reduced construction costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If poly-silicon is used for active memory cell channels, then manufacturing is easier, but cell-to-cell performance variations increase and drive capabilities decrease
Solution Approach 1:
The patent changes the material parameter from poly-silicon to monocrystalline silicon for the channel region. This parameter change fundamentally improves carrier mobility and reduces performance variations between cells, directly resolving the contradiction between ease of manufacture and reliability by accepting the additional processing steps required for monocrystalline formation.
Solution Approach 2:
The patent employs a composite structure where monocrystalline silicon is used specifically for the channel region while other parts of the device may use different materials. This selective material composition optimizes the channel performance for low variation and high drive capability while maintaining overall device manufacturability.
2Productivity
If transistors are scaled down, then transistor performance and density improve, but wire performance degrades
Solution Approach 1:
The patent transitions from planar 2D transistor scaling to three-dimensional stacked architectures. By stacking multiple transistor layers vertically, the device achieves higher density without further lateral scaling, thereby preventing the interconnect degradation that would result from continued miniaturization.
Solution Approach 2:
Instead of continuing to scale down transistor dimensions horizontally, the patent inverts the scaling approach by building upward in the vertical dimension. This inversion allows density improvement through stacking while maintaining larger, more reliable interconnect dimensions.
3Speed
If 3D stacking is implemented, then wire lengths are reduced and wiring delay is kept low, but device complexity increases
Solution Approach 1:
The patent implements 3D stacking by adding vertical layers to the device architecture. This dimensional transition reduces the horizontal distance signals must travel between functional blocks, thereby reducing wiring delay and improving speed despite the increased vertical complexity.
Solution Approach 2:
The patent organizes multiple transistor layers and interconnect levels in a nested vertical structure. Each layer is integrated within the three-dimensional stack, with interconnects routing signals between levels. This nested arrangement compactly packs high-density functionality while managing the complexity through systematic layer integration.
Data Source
AI summary
A 3D device, the device including: a first level including logic circuits; and a second level including a plurality of memory cells, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonds, and where the logic circuits include a programmable logic circuit.