3D Semiconductor Interconnect Layout for Dense MOSFET Stacking
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Solution Overview
Problem
As semiconductor devices are scaled down, the operating characteristics of MOSFETs deteriorate due to increased integration challenges, requiring innovative solutions to enhance performance and integration in three-dimensional semiconductor devices.
Innovation Solution
A three-dimensional semiconductor device design featuring a through conductive pattern that connects stacked source/drain patterns to upper and lower connection structures, formed from the same conductive layer as the gate electrode, allowing for minimized connection area and increased integration, while simplifying the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional MOSFET scaling is continued, then device integration density increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar two-dimensional MOSFET architecture to a three-dimensional stacked architecture where multiple source/drain patterns are vertically stacked above each other. This dimensional change allows increased integration density while maintaining acceptable operating characteristics through the through conductive patterns that provide optimized electrical connections through the stacked structure.
Solution Approach 2:
The device is segmented into multiple discrete source/drain patterns stacked vertically, with each pattern connected to connection structures through dedicated through conductive patterns. This segmentation allows independent optimization of each stacked component and improves overall device performance by distributing electrical connections through multiple pathways.
2Area of stationary object
If connection area is minimized for increased integration, then device density improves, but fabrication complexity increases
Solution Approach 1:
The through conductive patterns are formed from the same conductive layer material as the gate electrode, merging two previously separate fabrication processes into one. This integration minimizes the number of fabrication steps while achieving both small connection area and reduced fabrication complexity.
Solution Approach 2:
The conductive layer serves multiple functions: it forms both the gate electrode and the through conductive patterns that connect stacked source/drain patterns to connection structures. This multi-functionality reduces the total number of materials and process steps required, simplifying fabrication while maintaining compact design.
Data Source
AI summary
A three-dimensional semiconductor device includes a lower connection structure; a device structure; and an upper connection structure sequentially disposed along a first direction, wherein the device structure includes a substrate on the lower connection structure; first and second source/drain patterns on the substrate; a separation pattern adjacent in a second direction to the source/drain patterns, the second direction being parallel to a bottom surface of the substrate; and a through conductive pattern adjacent in a third direction to the separation pattern, the third direction being parallel to the bottom surface of the substrate and intersecting the second direction, the through conductive pattern connects the lower connection structure and the upper connection structure to each other, and the through conductive pattern is connected either through the lower connection structure to the first source/drain pattern or through the upper connection structure to the second source/drain pattern.