3D Semiconductor Device With Nanometer-Sized Vertical Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D Integrated Circuit (IC) technologies face challenges in achieving high transistor performance and density due to limitations in interconnect wiring, wafer alignment, and processing temperatures, leading to inefficiencies in device scaling and increased costs.
Innovation Solution
The development of a 3D semiconductor device with multiple metal layers and single crystal silicon layers, utilizing a layer transfer process to create high-density interconnects through nanometer-sized vias, allowing for efficient electrical coupling between layers while maintaining low processing temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If Through Silicon Vias (TSV) are used to connect bonded wafers, then electrical connections between layers are achieved, but the density of interconnects is limited due to large landing pads requirements and large via diameters
Solution Approach 1:
The patent transitions from planar 2D interconnects to 3D vertical interconnects by stacking multiple semiconductor layers. Through-silicon vias (TSVs) enable vertical electrical connections through the thickness of the substrate, adding the z-dimension to interconnect routing. This dimensional change allows multiple interconnect levels to be stacked vertically, dramatically increasing interconnect density without requiring proportionally larger landing pads, as the vertical path provides additional routing capacity.
Solution Approach 2:
The patent segments the monolithic substrate into multiple thin semiconductor layers separated by insulating layers. Each layer can be processed independently and then bonded together, allowing TSVs to be formed in each layer separately. This segmentation enables higher interconnect density by distributing connections across multiple layers rather than requiring all connections to be made in a single plane, reducing the burden on any single landing pad.
2Productivity
If device dimensions are reduced to nanometer scale to improve performance and reduce cost, then device speed increases and area decreases, but interconnection wiring becomes the dominant limitation
Solution Approach 1:
The patent addresses the interconnect bottleneck by moving from planar 2D wiring to 3D vertical wiring structures. TSVs provide direct vertical pathways through the substrate, dramatically shortening interconnect lengths compared to lateral routing in scaled devices. This dimensional change decouples device scaling from interconnect scaling, allowing nanometer-scale transistors to maintain efficient electrical connections without the wiring complexity that normally dominates at small dimensions.
3Speed
If 3D integrated circuits are implemented with stacked active layers, then interconnect wiring length is reduced and performance improves, but manufacturing complexity and processing challenges increase
Solution Approach 1:
The patent divides the 3D IC structure into multiple independently processable semiconductor layers, each typically 2-10 micrometers thick. These thin layers can be manufactured using standard planar CMOS processing techniques, then separately bonded together with precise alignment. This segmentation approach enables complex 3D structures to be built from simpler, well-understood 2D processing steps, managing manufacturing complexity while achieving short interconnect paths and high performance.
Data Source
AI summary
A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level, where the second level overlays the first level and includes a plurality of second transistors; a fourth metal layer overlaying the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level and has a diameter of less than 500 nm and greater than 5 nm, where the third metal layer is connected to provide a power or ground signal to at least one of the second transistors.